2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/sizes.h>
30 #include <asm/arch/at91sam9_smc.h>
31 #include <asm/arch/at91_common.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_rstc.h>
34 #include <asm/arch/at91_matrix.h>
35 #include <asm/arch/clk.h>
36 #include <asm/arch/gpio.h>
39 #include <atmel_lcdc.h>
40 #include <dataflash.h>
41 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
46 DECLARE_GLOBAL_DATA_PTR;
48 /* ------------------------------------------------------------------------- */
50 * Miscelaneous platform dependent initialisations
53 #ifdef CONFIG_CMD_NAND
54 static void pm9261_nand_hw_init(void)
57 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
58 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
59 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
62 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
63 writel(csa, &matrix->csa);
65 /* Configure SMC CS3 for NAND/SmartMedia */
66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
79 #ifdef CONFIG_SYS_NAND_DBW_16
80 AT91_SMC_MODE_DBW_16 |
81 #else /* CONFIG_SYS_NAND_DBW_8 */
84 AT91_SMC_MODE_TDF_CYCLE(2),
87 writel(1 << ATMEL_ID_PIOA |
91 /* Configure RDY/BSY */
92 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
94 /* Enable NandFlash */
95 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
97 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
98 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
103 #ifdef CONFIG_DRIVER_DM9000
104 static void pm9261_dm9000_hw_init(void)
106 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
107 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
109 /* Configure SMC CS2 for DM9000 */
110 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
111 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
114 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
115 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
118 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
121 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
122 AT91_SMC_MODE_EXNW_DISABLE |
123 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
124 AT91_SMC_MODE_TDF_CYCLE(1),
127 /* Configure Interrupt pin as input, no pull-up */
128 writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
129 at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
134 vidinfo_t panel_info = {
138 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
139 ATMEL_LCDC_INVFRAME_INVERTED,
148 mmio: ATMEL_BASE_LCDC,
151 void lcd_enable(void)
153 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
156 void lcd_disable(void)
158 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
161 static void pm9261_lcd_hw_init(void)
163 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
165 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
166 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
167 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
168 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
169 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
170 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
171 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
172 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
173 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
174 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
175 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
176 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
177 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
178 at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
179 at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
180 at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
181 at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
182 at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
183 at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
184 at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
185 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
186 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
188 writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
190 gd->fb_base = ATMEL_BASE_SRAM;
193 #ifdef CONFIG_LCD_INFO
197 extern flash_info_t flash_info[];
199 void lcd_show_board_info(void)
201 ulong dram_size, nand_size, flash_size, dataflash_size;
205 lcd_printf ("%s\n", U_BOOT_VERSION);
206 lcd_printf ("(C) 2009 Ronetix GmbH\n");
207 lcd_printf ("support@ronetix.at\n");
208 lcd_printf ("%s CPU at %s MHz",
209 CONFIG_SYS_AT91_CPU_NAME,
210 strmhz(temp, get_cpu_clk_rate()));
213 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
214 dram_size += gd->bd->bi_dram[i].size;
217 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
218 nand_size += nand_info[i].size;
221 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
222 flash_size += flash_info[i].size;
225 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
226 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
227 dataflash_info[i].Device.pages_size;
229 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
230 "%ld MB DataFlash\n",
234 dataflash_size >> 20);
236 #endif /* CONFIG_LCD_INFO */
238 #endif /* CONFIG_LCD */
242 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
247 writel(1 << ATMEL_ID_PIOA |
251 /* adress of boot parameters */
252 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
254 at91_seriald_hw_init();
255 #ifdef CONFIG_CMD_NAND
256 pm9261_nand_hw_init();
258 #ifdef CONFIG_HAS_DATAFLASH
259 at91_spi0_hw_init(1 << 0);
261 #ifdef CONFIG_DRIVER_DM9000
262 pm9261_dm9000_hw_init();
265 pm9261_lcd_hw_init();
270 #ifdef CONFIG_DRIVER_DM9000
271 int board_eth_init(bd_t *bis)
273 return dm9000_initialize(bis);
279 /* dram_init must store complete ramsize in gd->ram_size */
280 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
285 void dram_init_banksize(void)
287 gd->bd->bi_dram[0].start = PHYS_SDRAM;
288 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
291 #ifdef CONFIG_RESET_PHY_R
294 #ifdef CONFIG_DRIVER_DM9000
296 * Initialize ethernet HW addr prior to starting Linux,
304 #ifdef CONFIG_DISPLAY_BOARDINFO
305 int checkboard (void)
309 printf ("Board : Ronetix PM9261\n");
310 printf ("Crystal frequency: %8s MHz\n",
311 strmhz(buf, get_main_clk_rate()));
312 printf ("CPU clock : %8s MHz\n",
313 strmhz(buf, get_cpu_clk_rate()));
314 printf ("Master clock : %8s MHz\n",
315 strmhz(buf, get_mck_clk_rate()));