2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/sizes.h>
29 #include <asm/arch/at91sam9263.h>
30 #include <asm/arch/at91sam9_smc.h>
31 #include <asm/arch/at91_common.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_rstc.h>
34 #include <asm/arch/at91_matrix.h>
35 #include <asm/arch/at91_pio.h>
36 #include <asm/arch/clk.h>
37 #include <asm/arch/io.h>
38 #include <asm/arch/hardware.h>
40 #include <atmel_lcdc.h>
41 #include <dataflash.h>
42 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
47 DECLARE_GLOBAL_DATA_PTR;
49 /* ------------------------------------------------------------------------- */
51 * Miscelaneous platform dependent initialisations
54 #ifdef CONFIG_CMD_NAND
55 static void pm9263_nand_hw_init(void)
58 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
59 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
62 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
63 writel(csa, &matrix->csa[0]);
65 /* Configure SMC CS3 for NAND/SmartMedia */
66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
79 #ifdef CONFIG_SYS_NAND_DBW_16
80 AT91_SMC_MODE_DBW_16 |
81 #else /* CONFIG_SYS_NAND_DBW_8 */
84 AT91_SMC_MODE_TDF_CYCLE(2),
87 /* Configure RDY/BSY */
88 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
90 /* Enable NandFlash */
91 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
96 static void pm9263_macb_hw_init(void)
98 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
101 * PB27 enables the 50MHz oscillator for Ethernet PHY
105 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
106 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
109 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
112 * Disable pull-up on:
113 * RXDV (PC25) => PHY normal mode (not Test mode)
114 * ERX0 (PE25) => PHY ADDR0
115 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
117 * PHY has internal pull-down
120 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
121 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
122 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
124 /* Re-enable pull-up */
125 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
126 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
127 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
134 vidinfo_t panel_info = {
138 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
139 ATMEL_LCDC_INVFRAME_INVERTED,
148 mmio: AT91SAM9263_LCDC_BASE,
151 void lcd_enable(void)
153 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
156 void lcd_disable(void)
158 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
161 #ifdef CONFIG_LCD_IN_PSRAM
163 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
164 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
166 /* Initialize the PSRAM memory */
167 static int pm9263_lcd_hw_psram_init(void)
171 at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE;
172 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
174 /* Enable CS3 3.3v, no pull-ups */
175 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
176 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
178 writel(csa, &matrix->csa[1]);
180 /* Configure SMC1 CS0 for PSRAM - 16-bit */
181 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
182 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
185 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
186 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
189 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
192 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
195 /* setup PB29 as output */
196 at91_set_pio_output(PSRAM_CRE_PIN, 1);
198 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
200 /* PSRAM: write BCR */
201 x = readw(PSRAM_CTRL_REG);
202 x = readw(PSRAM_CTRL_REG);
203 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
204 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
206 /* write RCR of the PSRAM */
207 x = readw(PSRAM_CTRL_REG);
208 x = readw(PSRAM_CTRL_REG);
209 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
210 /* set RCR; 0x10-async mode,0x90-page mode */
211 writew(0x90, PSRAM_CTRL_REG);
214 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
215 * MT45W2M16B - CRE must be 0
216 * MT45W2M16A - CRE must be 1
218 writew(0x1234, PHYS_PSRAM);
219 writew(0x5678, PHYS_PSRAM + 2);
221 /* test if the chip is MT45W2M16B */
222 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
223 /* try with CRE=1 (MT45W2M16A) */
224 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
226 /* write RCR of the PSRAM */
227 x = readw(PSRAM_CTRL_REG);
228 x = readw(PSRAM_CTRL_REG);
229 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
230 /* set RCR;0x10-async mode,0x90-page mode */
231 writew(0x90, PSRAM_CTRL_REG);
234 writew(0x1234, PHYS_PSRAM);
235 writew(0x5678, PHYS_PSRAM+2);
236 if ((readw(PHYS_PSRAM) != 0x1234)
237 || (readw(PHYS_PSRAM + 2) != 0x5678))
243 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
244 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
250 static void pm9263_lcd_hw_init(void)
252 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
254 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
255 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
256 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
257 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
258 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
259 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
260 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
261 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
262 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
263 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
264 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
265 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
266 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
267 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
268 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
269 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
270 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
271 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
272 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
273 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
274 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
275 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
276 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
278 writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
281 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
282 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
284 #ifdef CONFIG_LCD_IN_PSRAM
285 /* initialize te PSRAM */
286 int stat = pm9263_lcd_hw_psram_init();
288 gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
290 gd->fb_base = AT91SAM9263_SRAM0_BASE;
295 #ifdef CONFIG_LCD_INFO
299 extern flash_info_t flash_info[];
301 void lcd_show_board_info(void)
303 ulong dram_size, nand_size, flash_size, dataflash_size;
307 lcd_printf ("%s\n", U_BOOT_VERSION);
308 lcd_printf ("(C) 2009 Ronetix GmbH\n");
309 lcd_printf ("support@ronetix.at\n");
310 lcd_printf ("%s CPU at %s MHz",
311 CONFIG_SYS_AT91_CPU_NAME,
312 strmhz(temp, get_cpu_clk_rate()));
315 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
316 dram_size += gd->bd->bi_dram[i].size;
319 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
320 nand_size += nand_info[i].size;
323 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
324 flash_size += flash_info[i].size;
327 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
328 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
329 dataflash_info[i].Device.pages_size;
331 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
332 "4 MB PSRAM, %ld MB DataFlash\n",
336 dataflash_size >> 20);
338 #endif /* CONFIG_LCD_INFO */
340 #endif /* CONFIG_LCD */
344 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
349 writel((1 << AT91SAM9263_ID_PIOA) |
350 (1 << AT91SAM9263_ID_PIOCDE) |
351 (1 << AT91SAM9263_ID_PIOB),
354 /* arch number of AT91SAM9263EK-Board */
355 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
357 /* adress of boot parameters */
358 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
360 at91_serial_hw_init();
361 #ifdef CONFIG_CMD_NAND
362 pm9263_nand_hw_init();
364 #ifdef CONFIG_HAS_DATAFLASH
365 at91_spi0_hw_init(1 << 0);
368 pm9263_macb_hw_init();
370 #ifdef CONFIG_USB_OHCI_NEW
374 pm9263_lcd_hw_init();
381 gd->bd->bi_dram[0].start = PHYS_SDRAM;
382 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
386 #ifdef CONFIG_RESET_PHY_R
392 int board_eth_init(bd_t *bis)
396 rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
401 #ifdef CONFIG_DISPLAY_BOARDINFO
402 int checkboard (void)
406 printf ("Board : Ronetix PM9263\n");
408 switch (gd->fb_base) {
413 case AT91SAM9263_SRAM0_BASE:
414 ss = "(Internal SRAM)";
421 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );