2 * Machine Specific Values for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _SMDK5250_SETUP_H
26 #define _SMDK5250_SETUP_H
29 #include <asm/arch/dmc.h>
31 /* TZPC : Register Offsets */
32 #define TZPC0_BASE 0x10100000
33 #define TZPC1_BASE 0x10110000
34 #define TZPC2_BASE 0x10120000
35 #define TZPC3_BASE 0x10130000
36 #define TZPC4_BASE 0x10140000
37 #define TZPC5_BASE 0x10150000
38 #define TZPC6_BASE 0x10160000
39 #define TZPC7_BASE 0x10170000
40 #define TZPC8_BASE 0x10180000
41 #define TZPC9_BASE 0x10190000
44 #define APLL_CON1_VAL (0x00203800)
47 #define MPLL_CON1_VAL (0x00203800)
50 #define CPLL_CON1_VAL (0x00203800)
53 #define GPLL_CON1_VAL (0x00203800)
56 #define EPLL_CON1_VAL 0x00000000
57 #define EPLL_CON2_VAL 0x00000080
60 #define VPLL_CON1_VAL 0x00000000
61 #define VPLL_CON2_VAL 0x00000080
64 #define BPLL_CON1_VAL 0x00203800
67 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
70 /* 0 = MOUTAPLL, 1 = SCLKMPLL */
73 #define MUX_APLL_SEL 1
75 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
76 | (MUX_CPU_SEL << 16) \
79 /* MEMCONTROL register bit fields */
80 #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
81 #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
82 #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
83 #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
84 #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
85 #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
86 #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
88 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
89 #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
90 #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
92 #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
94 #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
95 #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
97 #define DMC_MEMCONTROL_BL_8 (3 << 20)
98 #define DMC_MEMCONTROL_BL_4 (2 << 20)
100 #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
102 #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
103 #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
104 #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
105 #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
107 /* MEMCONFIG0 register bit fields */
108 #define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
109 #define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
110 #define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
111 #define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
112 #define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
114 #define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
115 #define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
116 #define DMC_MEMBASECONFIG_VAL(x) ( \
117 DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
118 DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
121 #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
122 #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
124 #define DMC_PRECHCONFIG_VAL 0xFF000000
125 #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
127 #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
128 #define DFI_INIT_START (1 << 28)
129 #define EMPTY (1 << 8)
130 #define AREF_EN (1 << 5)
132 #define DFI_INIT_COMPLETE_CHO (1 << 2)
133 #define DFI_INIT_COMPLETE_CH1 (1 << 3)
135 #define RDLVL_COMPLETE_CHO (1 << 14)
136 #define RDLVL_COMPLETE_CH1 (1 << 15)
138 #define CLK_STOP_EN (1 << 0)
139 #define DPWRDN_EN (1 << 1)
140 #define DSREF_EN (1 << 5)
142 /* COJCONTROL register bit fields */
143 #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
144 #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
145 #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
146 #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
147 #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
148 #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
149 #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
151 /* CLK_DIV_CPU0_VAL */
152 #define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
153 | (APLL_RATIO << 24) \
154 | (PCLK_DBG_RATIO << 20) \
155 | (ATB_RATIO << 16) \
156 | (PERIPH_RATIO << 12) \
158 | (CPUD_RATIO << 4) \
163 #define CLK_SRC_FSYS0_VAL 0x66666
164 #define CLK_DIV_FSYS0_VAL 0x0BB00000
167 #define HPM_RATIO 0x2
168 #define COPY_RATIO 0x0
170 /* CLK_DIV_CPU1 = 0x00000003 */
171 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
175 #define CLK_SRC_CORE0_VAL 0x00000000
178 #define CLK_SRC_CORE1_VAL 0x100
181 #define CLK_DIV_CORE0_VAL 0x00120000
184 #define CLK_DIV_CORE1_VAL 0x07070700
187 #define CLK_DIV_SYSRGT_VAL 0x00000111
190 #define CLK_DIV_ACP_VAL 0x12
193 #define CLK_DIV_SYSLFT_VAL 0x00000311
196 #define CLK_SRC_CDREX_VAL 0x1
199 #define MCLK_CDREX2_RATIO 0x0
200 #define ACLK_EFCON_RATIO 0x1
201 #define MCLK_DPHY_RATIO 0x1
202 #define MCLK_CDREX_RATIO 0x1
203 #define ACLK_C2C_200_RATIO 0x1
204 #define C2C_CLK_400_RATIO 0x1
205 #define PCLK_CDREX_RATIO 0x1
206 #define ACLK_CDREX_RATIO 0x1
208 #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
209 | (C2C_CLK_400_RATIO << 6) \
210 | (PCLK_CDREX_RATIO << 4) \
211 | (ACLK_CDREX_RATIO))
214 #define MUX_ACLK_300_GSCL_SEL 0x0
215 #define MUX_ACLK_300_GSCL_MID_SEL 0x0
216 #define MUX_ACLK_400_G3D_MID_SEL 0x0
217 #define MUX_ACLK_333_SEL 0x0
218 #define MUX_ACLK_300_DISP1_SEL 0x0
219 #define MUX_ACLK_300_DISP1_MID_SEL 0x0
220 #define MUX_ACLK_200_SEL 0x0
221 #define MUX_ACLK_166_SEL 0x0
222 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
223 | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
224 | (MUX_ACLK_400_G3D_MID_SEL << 20) \
225 | (MUX_ACLK_333_SEL << 16) \
226 | (MUX_ACLK_300_DISP1_SEL << 15) \
227 | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
228 | (MUX_ACLK_200_SEL << 12) \
229 | (MUX_ACLK_166_SEL << 8))
232 #define MUX_ACLK_400_G3D_SEL 0x1
233 #define MUX_ACLK_400_ISP_SEL 0x0
234 #define MUX_ACLK_400_IOP_SEL 0x0
235 #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
236 #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
237 #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
238 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
239 |(MUX_ACLK_400_ISP_SEL << 24) \
240 |(MUX_ACLK_400_IOP_SEL << 20) \
241 |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
242 |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
243 |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
246 #define MUX_GPLL_SEL 0x1
247 #define MUX_BPLL_USER_SEL 0x0
248 #define MUX_MPLL_USER_SEL 0x0
249 #define MUX_VPLL_SEL 0x1
250 #define MUX_EPLL_SEL 0x1
251 #define MUX_CPLL_SEL 0x1
252 #define VPLLSRC_SEL 0x0
253 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
254 | (MUX_BPLL_USER_SEL << 24) \
255 | (MUX_MPLL_USER_SEL << 20) \
256 | (MUX_VPLL_SEL << 16) \
257 | (MUX_EPLL_SEL << 12) \
258 | (MUX_CPLL_SEL << 8) \
261 #define MUX_ACLK_333_SUB_SEL 0x1
262 #define MUX_ACLK_400_SUB_SEL 0x1
263 #define MUX_ACLK_266_ISP_SUB_SEL 0x1
264 #define MUX_ACLK_266_GPS_SUB_SEL 0x0
265 #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
266 #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
267 #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
268 #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
269 #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
270 | (MUX_ACLK_400_SUB_SEL << 20) \
271 | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
272 | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
273 | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
274 | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
275 | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
276 | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
279 #define ACLK_300_DISP1_RATIO 0x2
280 #define ACLK_400_G3D_RATIO 0x0
281 #define ACLK_333_RATIO 0x0
282 #define ACLK_266_RATIO 0x2
283 #define ACLK_200_RATIO 0x3
284 #define ACLK_166_RATIO 0x1
285 #define ACLK_133_RATIO 0x1
286 #define ACLK_66_RATIO 0x5
288 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
289 | (ACLK_400_G3D_RATIO << 24) \
290 | (ACLK_333_RATIO << 20) \
291 | (ACLK_266_RATIO << 16) \
292 | (ACLK_200_RATIO << 12) \
293 | (ACLK_166_RATIO << 8) \
294 | (ACLK_133_RATIO << 4) \
298 #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
299 #define ACLK_66_PRE_RATIO 0x1
300 #define ACLK_400_ISP_RATIO 0x1
301 #define ACLK_400_IOP_RATIO 0x1
302 #define ACLK_300_GSCL_RATIO 0x2
304 #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
305 | (ACLK_66_PRE_RATIO << 24) \
306 | (ACLK_400_ISP_RATIO << 20) \
307 | (ACLK_400_IOP_RATIO << 16) \
308 | (ACLK_300_GSCL_RATIO << 12))
311 #define APLL_LOCK_VAL (0x546)
313 #define MPLL_LOCK_VAL (0x546)
315 #define CPLL_LOCK_VAL (0x546)
317 #define GPLL_LOCK_VAL (0x546)
319 #define EPLL_LOCK_VAL (0x3A98)
321 #define VPLL_LOCK_VAL (0x3A98)
323 #define BPLL_LOCK_VAL (0x546)
325 #define MUX_APLL_SEL_MASK (1 << 0)
326 #define MUX_MPLL_SEL_MASK (1 << 8)
327 #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
328 #define MUX_CPLL_SEL_MASK (1 << 8)
329 #define MUX_EPLL_SEL_MASK (1 << 12)
330 #define MUX_VPLL_SEL_MASK (1 << 16)
331 #define MUX_GPLL_SEL_MASK (1 << 28)
332 #define MUX_BPLL_SEL_MASK (1 << 0)
333 #define MUX_HPM_SEL_MASK (1 << 20)
334 #define HPM_SEL_SCLK_MPLL (1 << 21)
335 #define APLL_CON0_LOCKED (1 << 29)
336 #define MPLL_CON0_LOCKED (1 << 29)
337 #define BPLL_CON0_LOCKED (1 << 29)
338 #define CPLL_CON0_LOCKED (1 << 29)
339 #define EPLL_CON0_LOCKED (1 << 29)
340 #define GPLL_CON0_LOCKED (1 << 29)
341 #define VPLL_CON0_LOCKED (1 << 29)
342 #define CLK_REG_DISABLE 0x0
343 #define TOP2_VAL 0x0110000
351 /* SRC_CLOCK = SCLK_MPLL */
352 #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
353 | (UART3_SEL << 12) \
359 /* SRC_CLOCK = SCLK_MPLL */
363 #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
367 /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
368 #define SPI0_ISP_SEL 6
369 #define SPI1_ISP_SEL 6
370 #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
371 | (SPI0_ISP_SEL << 0)
373 /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
374 #define SPI0_ISP_RATIO 0xf
375 #define SPI1_ISP_RATIO 0xf
376 #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
377 | (SPI0_ISP_RATIO << 0)
380 #define UART5_RATIO 7
381 #define UART4_RATIO 7
382 #define UART3_RATIO 7
383 #define UART2_RATIO 7
384 #define UART1_RATIO 7
385 #define UART0_RATIO 7
387 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
388 | (UART2_RATIO << 8) \
389 | (UART1_RATIO << 4) \
392 #define SPI1_RATIO 0x7
393 #define SPI0_RATIO 0xf
394 #define SPI1_SUB_RATIO 0x0
395 #define SPI0_SUB_RATIO 0x0
396 #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
397 | ((SPI1_RATIO << 16) \
398 | (SPI0_SUB_RATIO << 8) \
399 | (SPI0_RATIO << 0)))
402 #define SPI2_RATIO 0xf
403 #define SPI2_SUB_RATIO 0x0
404 #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
409 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
412 #define MMC2_RATIO_MASK 0xf
413 #define MMC2_RATIO_VAL 0x3
414 #define MMC2_RATIO_OFFSET 0
416 #define MMC2_PRE_RATIO_MASK 0xff
417 #define MMC2_PRE_RATIO_VAL 0x9
418 #define MMC2_PRE_RATIO_OFFSET 8
420 #define MMC3_RATIO_MASK 0xf
421 #define MMC3_RATIO_VAL 0x1
422 #define MMC3_RATIO_OFFSET 16
424 #define MMC3_PRE_RATIO_MASK 0xff
425 #define MMC3_PRE_RATIO_VAL 0x0
426 #define MMC3_PRE_RATIO_OFFSET 24
429 #define CLK_SRC_LEX_VAL 0x0
432 #define CLK_DIV_LEX_VAL 0x10
435 #define CLK_DIV_R0X_VAL 0x10
438 #define CLK_DIV_R1X_VAL 0x10
441 #define CLK_DIV_ISP0_VAL 0x31
444 #define CLK_DIV_ISP1_VAL 0x0
447 #define CLK_DIV_ISP2_VAL 0x1
449 /* CLK_SRC_DISP1_0 */
450 #define CLK_SRC_DISP1_0_VAL 0x6
454 * For DP, divisor should be 2
456 #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
458 /* CLK_GATE_IP_DISP1 */
459 #define CLK_GATE_DP1_ALLOW (1 << 4)
462 * TZPC Register Value :
463 * R0SIZE: 0x0 : Size of secured ram
468 * TZPC Decode Protection Register Value :
469 * DECPROTXSET: 0xFF : Set Decode region to non-secure
471 #define DECPROTXSET 0xFF
473 #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
474 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
476 #define PHY_CON0_RESET_VAL 0x17020a40
477 #define P0_CMD_EN (1 << 14)
478 #define BYTE_RDLVL_EN (1 << 13)
479 #define CTRL_SHGATE (1 << 8)
481 #define PHY_CON1_RESET_VAL 0x09210100
482 #define CTRL_GATEDURADJ_MASK (0xf << 20)
484 #define PHY_CON2_RESET_VAL 0x00010004
485 #define INIT_DESKEW_EN (1 << 6)
486 #define RDLVL_GATE_EN (1 << 24)
488 /*ZQ Configurations */
489 #define PHY_CON16_RESET_VAL 0x08000304
491 #define ZQ_CLK_DIV_EN (1 << 18)
492 #define ZQ_MANUAL_STR (1 << 1)
493 #define ZQ_DONE (1 << 0)
495 #define CTRL_RDLVL_GATE_ENABLE 1
496 #define CTRL_RDLVL_GATE_DISABLE 1
499 #define DIRECT_CMD_NOP 0x07000000
500 #define DIRECT_CMD_PALL 0x01000000
501 #define DIRECT_CMD_ZQINIT 0x0a000000
502 #define DIRECT_CMD_CHANNEL_SHIFT 28
503 #define DIRECT_CMD_CHIP_SHIFT 20
505 /* DMC PHY Control0 register */
506 #define PHY_CONTROL0_RESET_VAL 0x0
507 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
508 #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
509 #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
510 #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
512 /* Driver strength for CK, CKE, CS & CA */
513 #define IMP_OUTPUT_DRV_40_OHM 0x5
514 #define IMP_OUTPUT_DRV_30_OHM 0x7
515 #define CA_CK_DRVR_DS_OFFSET 9
516 #define CA_CKE_DRVR_DS_OFFSET 6
517 #define CA_CS_DRVR_DS_OFFSET 3
518 #define CA_ADR_DRVR_DS_OFFSET 0
520 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
521 #define PHY_CON42_CTRL_RDLAT_SHIFT 0
525 /* Errors that we can encourter in low-level setup */
528 SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
529 SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
533 * Memory variant specific initialization code
535 * @param mem Memory timings for this memory type.
536 * @param mem_iv_size Memory interleaving size is a configurable parameter
537 * which the DMC uses to decide how to split a memory
538 * chunk into smaller chunks to support concurrent
539 * accesses; may vary across boards.
540 * @return 0 if ok, SETUP_ERR_... if there is a problem
542 int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
545 * Configure ZQ I/O interface
547 * @param mem Memory timings for this memory type.
548 * @param phy0_ctrl Pointer to struct containing PHY0 control reg
549 * @param phy1_ctrl Pointer to struct containing PHY1 control reg
550 * @return 0 if ok, -1 on error
552 int dmc_config_zq(struct mem_timings *mem,
553 struct exynos5_phy_control *phy0_ctrl,
554 struct exynos5_phy_control *phy1_ctrl);
557 * Send NOP and MRS/EMRS Direct commands
559 * @param mem Memory timings for this memory type.
560 * @param dmc Pointer to struct of DMC registers
562 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
565 * Send PALL Direct commands
567 * @param mem Memory timings for this memory type.
568 * @param dmc Pointer to struct of DMC registers
570 void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
573 * Configure the memconfig and membaseconfig registers
575 * @param mem Memory timings for this memory type.
576 * @param exynos5_dmc Pointer to struct of DMC registers
578 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
581 * Reset the DLL. This function is common between DDR3 and LPDDR2.
582 * However, the reset value is different. So we are passing a flag
583 * ddr_mode to distinguish between LPDDR2 and DDR3.
585 * @param exynos5_dmc Pointer to struct of DMC registers
586 * @param ddr_mode Type of DDR memory
588 void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
590 void sdelay(unsigned long);
591 void mem_ctrl_init(void);
592 void system_clock_init(void);
593 void tzpc_init(void);