2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc.h>
29 #include <asm/arch/sromc.h>
31 DECLARE_GLOBAL_DATA_PTR;
32 struct exynos5_gpio_part1 *gpio1;
35 static void smc9115_pre_init(void)
37 u32 smc_bw_conf, smc_bc_conf;
44 * GPY0[1] SROM_CSn[1](2)
50 * GPY1[0] EBI_BEn[0](2)
51 * GPY1[1] EBI_BEn[1](2)
52 * GPY1[2] SROM_WAIT(2)
53 * GPY1[3] EBI_DATA_RDn(2)
55 s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
56 s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
57 s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
59 for (i = 0; i < 4; i++)
60 s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
65 * GPY3[0] EBI_ADDR[0](2)
66 * GPY3[1] EBI_ADDR[1](2)
67 * GPY3[2] EBI_ADDR[2](2)
68 * GPY3[3] EBI_ADDR[3](2)
69 * GPY3[4] EBI_ADDR[4](2)
70 * GPY3[5] EBI_ADDR[5](2)
71 * GPY3[6] EBI_ADDR[6](2)
72 * GPY3[7] EBI_ADDR[7](2)
76 * GPY5[0] EBI_DATA[0](2)
77 * GPY5[1] EBI_DATA[1](2)
78 * GPY5[2] EBI_DATA[2](2)
79 * GPY5[3] EBI_DATA[3](2)
80 * GPY5[4] EBI_DATA[4](2)
81 * GPY5[5] EBI_DATA[5](2)
82 * GPY5[6] EBI_DATA[6](2)
83 * GPY5[7] EBI_DATA[7](2)
85 * GPY6[0] EBI_DATA[8](2)
86 * GPY6[1] EBI_DATA[9](2)
87 * GPY6[2] EBI_DATA[10](2)
88 * GPY6[3] EBI_DATA[11](2)
89 * GPY6[4] EBI_DATA[12](2)
90 * GPY6[5] EBI_DATA[13](2)
91 * GPY6[6] EBI_DATA[14](2)
92 * GPY6[7] EBI_DATA[15](2)
94 for (i = 0; i < 8; i++) {
95 s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
96 s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
98 s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
99 s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
101 s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
102 s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
105 /* Ethernet needs data bus width of 16 bits */
106 smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
107 | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
109 smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
110 | SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
111 | SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
112 | SROMC_BC_PMC(0x01);
114 /* Select and configure the SROMC bank */
115 s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
121 gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
123 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
129 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
130 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
131 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
132 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
133 + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
134 + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
135 + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
136 + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
140 void dram_init_banksize(void)
142 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
143 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
145 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
146 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
148 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
149 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
151 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
152 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
154 gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
155 gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
157 gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
158 gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
160 gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
161 gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
163 gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
164 gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
168 int board_eth_init(bd_t *bis)
170 #ifdef CONFIG_SMC911X
172 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
177 #ifdef CONFIG_DISPLAY_BOARDINFO
180 printf("\nBoard: SMDK5250\n");
186 #ifdef CONFIG_GENERIC_MMC
187 int board_mmc_init(bd_t *bis)
194 * GPC2[0] SD_2_CLK(2)
195 * GPC2[1] SD_2_CMD(2)
197 * GPC2[3:6] SD_2_DATA[0:3](2)
199 for (i = 0; i < 7; i++) {
200 /* GPC2[0:6] special function 2 */
201 s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
203 /* GPK2[0:6] drv 4x */
204 s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
206 /* GPK2[0:1] pull disable */
207 if (i == 0 || i == 1) {
208 s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
212 /* GPK2[2:6] pull up */
213 s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
216 err = s5p_mmc_init(2, 4);
221 static void board_uart_init(void)
223 struct exynos5_gpio_part1 *gpio1 =
224 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
228 * UART0 GPIOs : GPA0CON[3:0] 0x2222
229 * Must set CFG17 switches to select UART0 to use.
231 for (i = 0; i <= 3; i++) {
232 s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
233 s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
237 * UART1 GPIOs : GPA0CON[5:4] 0x22
238 * Must set CFG17 switches to select UART1 to use.
240 * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
241 * in order to use them (so that those pins can be used for I2C).
243 for (i = 4; i <= 5; i++) {
244 s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
245 s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
249 * UART2 GPIOs : GPA1CON[1:0] 0x22
250 * Must set CFG17 switches to select UART2 to use.
252 * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
253 * in order to use them (so that those pins can be used for I2C).
255 for (i = 0; i <= 1; i++) {
256 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
257 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
261 * UART3 GPIOs : GPA1CON[5:4] 0x22
262 * Must set CFG16 switches to select UART3 to use.
264 for (i = 4; i <= 5; i++) {
265 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
266 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
270 * There's no mux for UART4--it's internal only
274 #ifdef CONFIG_BOARD_EARLY_INIT_F
275 int board_early_init_f(void)