2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/mmc.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/mipi_dsim.h>
35 #include <asm/arch/watchdog.h>
36 #include <asm/arch/power.h>
38 #include <usb/s3c_udc.h>
39 #include <max8997_pmic.h>
44 DECLARE_GLOBAL_DATA_PTR;
46 unsigned int board_rev;
48 #ifdef CONFIG_REVISION_TAG
49 u32 get_board_rev(void)
55 static void check_hw_revision(void);
57 static int hwrevision(int rev)
59 return (board_rev & 0xf) == rev;
64 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
67 printf("HW Revision:\t0x%x\n", board_rev);
69 #if defined(CONFIG_PMIC)
78 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
79 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
84 void dram_init_banksize(void)
86 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
87 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
88 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
89 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
92 static unsigned int get_hw_revision(void)
94 struct exynos4_gpio_part1 *gpio =
95 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
99 /* hw_rev[3:0] == GPE1[3:0] */
100 for (i = 0; i < 4; i++) {
101 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
102 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
107 for (i = 0; i < 4; i++)
108 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
110 debug("hwrev 0x%x\n", hwrev);
115 static void check_hw_revision(void)
119 hwrev = get_hw_revision();
124 #ifdef CONFIG_DISPLAY_BOARDINFO
127 puts("Board:\tTRATS\n");
132 #ifdef CONFIG_GENERIC_MMC
133 int board_mmc_init(bd_t *bis)
135 struct exynos4_gpio_part2 *gpio =
136 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
139 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
140 s5p_gpio_direction_output(&gpio->k0, 2, 1);
141 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
145 * SDR 8-bit@48MHz at MMC0
146 * GPK0[0] SD_0_CLK(2)
147 * GPK0[1] SD_0_CMD(2)
148 * GPK0[2] SD_0_CDn -> Not used
149 * GPK0[3:6] SD_0_DATA[0:3](2)
150 * GPK1[3:6] SD_0_DATA[0:3](3)
152 * DDR 4-bit@26MHz at MMC4
153 * GPK0[0] SD_4_CLK(3)
154 * GPK0[1] SD_4_CMD(3)
155 * GPK0[2] SD_4_CDn -> Not used
156 * GPK0[3:6] SD_4_DATA[0:3](3)
157 * GPK1[3:6] SD_4_DATA[4:7](4)
159 for (i = 0; i < 7; i++) {
162 /* GPK0[0:6] special function 2 */
163 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
164 /* GPK0[0:6] pull disable */
165 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
166 /* GPK0[0:6] drv 4x */
167 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
170 for (i = 3; i < 7; i++) {
171 /* GPK1[3:6] special function 3 */
172 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
173 /* GPK1[3:6] pull disable */
174 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
175 /* GPK1[3:6] drv 4x */
176 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
181 * mmc0 : eMMC (8-bit buswidth)
182 * mmc2 : SD card (4-bit buswidth)
184 err = s5p_mmc_init(0, 8);
187 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
188 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
191 * Check the T-flash detect pin
192 * GPX3[4] T-flash detect pin
194 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
197 * GPK2[0] SD_2_CLK(2)
198 * GPK2[1] SD_2_CMD(2)
199 * GPK2[2] SD_2_CDn -> Not used
200 * GPK2[3:6] SD_2_DATA[0:3](2)
202 for (i = 0; i < 7; i++) {
205 /* GPK2[0:6] special function 2 */
206 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
207 /* GPK2[0:6] pull disable */
208 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
209 /* GPK2[0:6] drv 4x */
210 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
212 err = s5p_mmc_init(2, 4);
219 #ifdef CONFIG_USB_GADGET
220 static int s5pc210_phy_control(int on)
223 struct pmic *p = get_pmic();
229 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
231 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO);
232 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO);
234 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO);
235 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO);
236 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
237 ENSAFEOUT1, LDO_OFF);
241 puts("MAX8997 LDO setting error!\n");
248 struct s3c_plat_otg_data s5pc210_otg_data = {
249 .phy_control = s5pc210_phy_control,
250 .regs_phy = EXYNOS4_USBPHY_BASE,
251 .regs_otg = EXYNOS4_USBOTG_BASE,
252 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
253 .usb_flags = PHY0_SLEEP,
257 static void pmic_reset(void)
259 struct exynos4_gpio_part2 *gpio =
260 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
262 s5p_gpio_direction_output(&gpio->x0, 7, 1);
263 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
266 static void board_clock_init(void)
268 struct exynos4_clock *clk =
269 (struct exynos4_clock *)samsung_get_base_clock();
271 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
272 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
273 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
274 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
276 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
277 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
278 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
279 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
280 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
281 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
282 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
283 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
284 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
285 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
286 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
287 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
289 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
290 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
291 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
292 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
293 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
294 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
295 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
296 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
297 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
298 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
299 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
300 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
302 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
303 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
304 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
305 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
306 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
307 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
308 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
309 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
310 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
311 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
312 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
313 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
316 static void board_power_init(void)
318 struct exynos4_power *pwr =
319 (struct exynos4_power *)samsung_get_base_power();
322 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
325 writel(0, (unsigned int)&pwr->cam_configuration);
326 writel(0, (unsigned int)&pwr->tv_configuration);
327 writel(0, (unsigned int)&pwr->mfc_configuration);
328 writel(0, (unsigned int)&pwr->g3d_configuration);
329 writel(0, (unsigned int)&pwr->lcd1_configuration);
330 writel(0, (unsigned int)&pwr->gps_configuration);
331 writel(0, (unsigned int)&pwr->gps_alive_configuration);
334 static void board_uart_init(void)
336 struct exynos4_gpio_part1 *gpio1 =
337 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
338 struct exynos4_gpio_part2 *gpio2 =
339 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
344 * GPA1CON[0] = UART_2_RXD(2)
345 * GPA1CON[1] = UART_2_TXD(2)
346 * GPA1CON[2] = I2C_3_SDA (3)
347 * GPA1CON[3] = I2C_3_SCL (3)
350 for (i = 0; i < 4; i++) {
351 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
352 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
355 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
356 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
357 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
360 int board_early_init_f(void)
371 static void lcd_reset(void)
373 struct exynos4_gpio_part2 *gpio2 =
374 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
376 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
378 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
380 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
383 static int lcd_power(void)
386 struct pmic *p = get_pmic();
391 /* LDO15 voltage: 2.2v */
392 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
393 /* LDO13 voltage: 3.0v */
394 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
397 puts("MAX8997 LDO setting error!\n");
404 static struct mipi_dsim_config dsim_config = {
405 .e_interface = DSIM_VIDEO,
406 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
407 .e_pixel_format = DSIM_24BPP_888,
408 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
409 .e_no_data_lane = DSIM_DATA_LANE_4,
410 .e_byte_clk = DSIM_PLL_OUT_DIV8,
417 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
418 .pll_stable_time = 500,
420 /* escape clk : 10MHz */
421 .esc_clk = 20 * 1000000,
423 /* stop state holding counter after bta change count 0 ~ 0xfff */
424 .stop_holding_cnt = 0x7ff,
425 /* bta timeout 0 ~ 0xff */
427 /* lp rx timeout 0 ~ 0xffff */
428 .rx_timeout = 0xffff,
431 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
432 .lcd_panel_info = NULL,
433 .dsim_config = &dsim_config,
436 static struct mipi_dsim_lcd_device mipi_lcd_device = {
440 .platform_data = (void *)&s6e8ax0_platform_data,
443 static int mipi_power(void)
446 struct pmic *p = get_pmic();
451 /* LDO3 voltage: 1.1v */
452 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
453 /* LDO4 voltage: 1.8v */
454 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
457 puts("MAX8997 LDO setting error!\n");
464 vidinfo_t panel_info = {
470 .vl_clkp = CONFIG_SYS_HIGH,
471 .vl_hsp = CONFIG_SYS_LOW,
472 .vl_vsp = CONFIG_SYS_LOW,
473 .vl_dp = CONFIG_SYS_LOW,
474 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
476 /* s6e8ax0 Panel infomation */
484 .vl_cmd_allow_len = 0xf,
488 .backlight_on = NULL,
489 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
490 .reset_lcd = lcd_reset,
491 .dual_lcd_enabled = 0,
496 .interface_mode = FIMD_RGB_INTERFACE,
500 void init_panel_info(vidinfo_t *vid)
503 vid->resolution = HD_RESOLUTION,
504 vid->rgb_mode = MODE_RGB_P,
507 get_tizen_logo_info(vid);
511 mipi_lcd_device.reverse_panel = 1;
513 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
514 s6e8ax0_platform_data.lcd_power = lcd_power;
515 s6e8ax0_platform_data.mipi_power = mipi_power;
516 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
517 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
518 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
520 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
522 setenv("lcdinfo", "lcd=s6e8ax0");