git.sur5r.net Git - u-boot/blob - board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <lcd.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/mipi_dsim.h>
  18 #include <asm/arch/watchdog.h>
  19 #include <asm/arch/power.h>
  20 #include <power/pmic.h>
  21 #include <usb/s3c_udc.h>
  22 #include <power/max8997_pmic.h>
  23 #include <power/max8997_muic.h>
  24 #include <power/battery.h>
  25 #include <power/max17042_fg.h>
  26 #include <libtizen.h>
  27 #include <usb.h>
  28 #include <usb_mass_storage.h>
  29
  30 #include "setup.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 unsigned int board_rev;
  35
  36 #ifdef CONFIG_REVISION_TAG
  37 u32 get_board_rev(void)
  38 {
  39         return board_rev;
  40 }
  41 #endif
  42
  43 static void check_hw_revision(void);
  44 struct s3c_plat_otg_data s5pc210_otg_data;
  45
  46 int exynos_init(void)
  47 {
  48         check_hw_revision();
  49         printf("HW Revision:\t0x%x\n", board_rev);
  50
  51         return 0;
  52 }
  53
  54 void i2c_init_board(void)
  55 {
  56         int err;
  57
  58         /* I2C_5 -> PMIC */
  59         err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
  60         if (err) {
  61                 debug("I2C%d not configured\n", (I2C_5));
  62                 return;
  63         }
  64
  65         /* I2C_8 -> FG */
  66         gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
  67         gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
  68 }
  69
  70 static void trats_low_power_mode(void)
  71 {
  72         struct exynos4_clock *clk =
  73             (struct exynos4_clock *)samsung_get_base_clock();
  74         struct exynos4_power *pwr =
  75             (struct exynos4_power *)samsung_get_base_power();
  76
  77         /* Power down CORE1 */
  78         /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
  79         writel(0x0, &pwr->arm_core1_configuration);
  80
  81         /* Change the APLL frequency */
  82         /* ENABLE (1 enable) | LOCKED (1 locked)  */
  83         /* [31]              | [29]               */
  84         /* FSEL      | MDIV          | PDIV            | SDIV */
  85         /* [27]      | [25:16]       | [13:8]          | [2:0]      */
  86         writel(0xa0c80604, &clk->apll_con0);
  87
  88         /* Change CPU0 clock divider */
  89         /* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
  90         /* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
  91         /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
  92         /* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
  93         writel(0x00000100, &clk->div_cpu0);
  94
  95         /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
  96         while (readl(&clk->div_stat_cpu0) & 0x1111111)
  97                 continue;
  98
  99         /* Change clock divider ratio for DMC */
 100         /* DMCP_RATIO                  | DMCD_RATIO  */
 101         /* [22:20]                     | [18:16]     */
 102         /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
 103         /* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
 104         writel(0x13113117, &clk->div_dmc0);
 105
 106         /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
 107         while (readl(&clk->div_stat_dmc0) & 0x11111111)
 108                 continue;
 109
 110         /* Turn off unnecessary power domains */
 111         writel(0x0, &pwr->xxti_configuration);  /* XXTI */
 112         writel(0x0, &pwr->cam_configuration);   /* CAM */
 113         writel(0x0, &pwr->tv_configuration);    /* TV */
 114         writel(0x0, &pwr->mfc_configuration);   /* MFC */
 115         writel(0x0, &pwr->g3d_configuration);   /* G3D */
 116         writel(0x0, &pwr->gps_configuration);   /* GPS */
 117         writel(0x0, &pwr->gps_alive_configuration);     /* GPS_ALIVE */
 118
 119         /* Turn off unnecessary clocks */
 120         writel(0x0, &clk->gate_ip_cam); /* CAM */
 121         writel(0x0, &clk->gate_ip_tv);          /* TV */
 122         writel(0x0, &clk->gate_ip_mfc); /* MFC */
 123         writel(0x0, &clk->gate_ip_g3d); /* G3D */
 124         writel(0x0, &clk->gate_ip_image);       /* IMAGE */
 125         writel(0x0, &clk->gate_ip_gps); /* GPS */
 126 }
 127
 128 static int pmic_init_max8997(void)
 129 {
 130         struct pmic *p = pmic_get("MAX8997_PMIC");
 131         int i = 0, ret = 0;
 132         u32 val;
 133
 134         if (pmic_probe(p))
 135                 return -1;
 136
 137         /* BUCK1 VARM: 1.2V */
 138         val = (1200000 - 650000) / 25000;
 139         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 140         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 141         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 142
 143         /* BUCK2 VINT: 1.1V */
 144         val = (1100000 - 650000) / 25000;
 145         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 146         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 147         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 148
 149
 150         /* BUCK3 G3D: 1.1V - OFF */
 151         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 152         val &= ~ENBUCK;
 153         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 154
 155         val = (1100000 - 750000) / 50000;
 156         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 157
 158         /* BUCK4 CAMISP: 1.2V - OFF */
 159         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 160         val &= ~ENBUCK;
 161         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 162
 163         val = (1200000 - 650000) / 25000;
 164         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 165
 166         /* BUCK5 VMEM: 1.2V */
 167         val = (1200000 - 650000) / 25000;
 168         for (i = 0; i < 8; i++)
 169                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 170
 171         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 172         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 173
 174         /* BUCK6 CAM AF: 2.8V */
 175         /* No Voltage Setting Register */
 176         /* GNSLCT 3.0X */
 177         val = GNSLCT;
 178         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 179
 180         /* BUCK7 VCC_SUB: 2.0V */
 181         val = (2000000 - 750000) / 50000;
 182         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 183
 184         /* LDO1 VADC: 3.3V */
 185         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 186         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 187
 188         /* LDO1 Disable active discharging */
 189         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 190         val &= ~LDO_ADE;
 191         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 192
 193         /* LDO2 VALIVE: 1.1V */
 194         val = max8997_reg_ldo(1100000) | EN_LDO;
 195         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 196
 197         /* LDO3 VUSB/MIPI: 1.1V */
 198         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 199         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 200
 201         /* LDO4 VMIPI: 1.8V */
 202         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 203         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 204
 205         /* LDO5 VHSIC: 1.2V */
 206         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 207         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 208
 209         /* LDO6 VCC_1.8V_PDA: 1.8V */
 210         val = max8997_reg_ldo(1800000) | EN_LDO;
 211         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 212
 213         /* LDO7 CAM_ISP: 1.8V */
 214         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 215         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 216
 217         /* LDO8 VDAC/VUSB: 3.3V */
 218         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 219         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 220
 221         /* LDO9 VCC_2.8V_PDA: 2.8V */
 222         val = max8997_reg_ldo(2800000) | EN_LDO;
 223         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 224
 225         /* LDO10 VPLL: 1.1V */
 226         val = max8997_reg_ldo(1100000) | EN_LDO;
 227         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 228
 229         /* LDO11 TOUCH: 2.8V */
 230         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 231         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 232
 233         /* LDO12 VTCAM: 1.8V */
 234         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 235         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 236
 237         /* LDO13 VCC_3.0_LCD: 3.0V */
 238         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 239         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 240
 241         /* LDO14 MOTOR: 3.0V */
 242         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 243         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 244
 245         /* LDO15 LED_A: 2.8V */
 246         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 247         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 248
 249         /* LDO16 CAM_SENSOR: 1.8V */
 250         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 251         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 252
 253         /* LDO17 VTF: 2.8V */
 254         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 255         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 256
 257         /* LDO18 TOUCH_LED 3.3V */
 258         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 259         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 260
 261         /* LDO21 VDDQ: 1.2V */
 262         val = max8997_reg_ldo(1200000) | EN_LDO;
 263         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 264
 265         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 266         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 267                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 268         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 269
 270         if (ret) {
 271                 puts("MAX8997 PMIC setting error!\n");
 272                 return -1;
 273         }
 274         return 0;
 275 }
 276
 277 int exynos_power_init(void)
 278 {
 279         int chrg, ret;
 280         struct power_battery *pb;
 281         struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
 282
 283         /*
 284          * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
 285          * to logical I2C adapter 0
 286          *
 287          * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 288          * to logical I2C adapter 1
 289          */
 290         ret = pmic_init(I2C_5);
 291         ret |= pmic_init_max8997();
 292         ret |= power_fg_init(I2C_9);
 293         ret |= power_muic_init(I2C_5);
 294         ret |= power_bat_init(0);
 295         if (ret)
 296                 return ret;
 297
 298         p_fg = pmic_get("MAX17042_FG");
 299         if (!p_fg) {
 300                 puts("MAX17042_FG: Not found\n");
 301                 return -ENODEV;
 302         }
 303
 304         p_chrg = pmic_get("MAX8997_PMIC");
 305         if (!p_chrg) {
 306                 puts("MAX8997_PMIC: Not found\n");
 307                 return -ENODEV;
 308         }
 309
 310         p_muic = pmic_get("MAX8997_MUIC");
 311         if (!p_muic) {
 312                 puts("MAX8997_MUIC: Not found\n");
 313                 return -ENODEV;
 314         }
 315
 316         p_bat = pmic_get("BAT_TRATS");
 317         if (!p_bat) {
 318                 puts("BAT_TRATS: Not found\n");
 319                 return -ENODEV;
 320         }
 321
 322         p_fg->parent =  p_bat;
 323         p_chrg->parent = p_bat;
 324         p_muic->parent = p_bat;
 325
 326         p_bat->low_power_mode = trats_low_power_mode;
 327         p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
 328
 329         pb = p_bat->pbat;
 330         chrg = p_muic->chrg->chrg_type(p_muic);
 331         debug("CHARGER TYPE: %d\n", chrg);
 332
 333         if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
 334                 puts("No battery detected\n");
 335                 return 0;
 336         }
 337
 338         p_fg->fg->fg_battery_check(p_fg, p_bat);
 339
 340         if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 341                 puts("CHARGE Battery !\n");
 342
 343         return 0;
 344 }
 345
 346 static unsigned int get_hw_revision(void)
 347 {
 348         int hwrev = 0;
 349         int i;
 350
 351         /* hw_rev[3:0] == GPE1[3:0] */
 352         for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) {
 353                 gpio_cfg_pin(i, S5P_GPIO_INPUT);
 354                 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 355         }
 356
 357         udelay(1);
 358
 359         for (i = 0; i < 4; i++)
 360                 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
 361
 362         debug("hwrev 0x%x\n", hwrev);
 363
 364         return hwrev;
 365 }
 366
 367 static void check_hw_revision(void)
 368 {
 369         int hwrev;
 370
 371         hwrev = get_hw_revision();
 372
 373         board_rev |= hwrev;
 374 }
 375
 376
 377 #ifdef CONFIG_USB_GADGET
 378 static int s5pc210_phy_control(int on)
 379 {
 380         int ret = 0;
 381         u32 val = 0;
 382         struct pmic *p = pmic_get("MAX8997_PMIC");
 383         if (!p)
 384                 return -ENODEV;
 385
 386         if (pmic_probe(p))
 387                 return -1;
 388
 389         if (on) {
 390                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 391                                       ENSAFEOUT1, LDO_ON);
 392                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 393                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 394
 395                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 396                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 397         } else {
 398                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 399                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 400
 401                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 402                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 403                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 404                                       ENSAFEOUT1, LDO_OFF);
 405         }
 406
 407         if (ret) {
 408                 puts("MAX8997 LDO setting error!\n");
 409                 return -1;
 410         }
 411
 412         return 0;
 413 }
 414
 415 struct s3c_plat_otg_data s5pc210_otg_data = {
 416         .phy_control    = s5pc210_phy_control,
 417         .regs_phy       = EXYNOS4_USBPHY_BASE,
 418         .regs_otg       = EXYNOS4_USBOTG_BASE,
 419         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 420         .usb_flags      = PHY0_SLEEP,
 421 };
 422
 423 int board_usb_init(int index, enum usb_init_type init)
 424 {
 425         debug("USB_udc_probe\n");
 426         return s3c_udc_probe(&s5pc210_otg_data);
 427 }
 428
 429 int g_dnl_board_usb_cable_connected(void)
 430 {
 431         struct pmic *muic = pmic_get("MAX8997_MUIC");
 432         if (!muic)
 433                 return 0;
 434
 435         return !!muic->chrg->chrg_type(muic);
 436 }
 437 #endif
 438
 439 static void pmic_reset(void)
 440 {
 441         gpio_direction_output(EXYNOS4_GPIO_X07, 1);
 442         gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
 443 }
 444
 445 static void board_clock_init(void)
 446 {
 447         struct exynos4_clock *clk =
 448                 (struct exynos4_clock *)samsung_get_base_clock();
 449
 450         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 451         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 452         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 453         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 454
 455         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 456         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 457         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 458         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 459         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 460         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 461         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 462         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 463         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 464         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 465         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 466         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 467
 468         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 469         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 470         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 471         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 472         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 473         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 474         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 475         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 476         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 477         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 478         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 479         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 480
 481         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 482         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 483         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 484         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 485         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 486         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 487         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 488         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 489         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 490         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 491         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 492         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 493 }
 494
 495 static void board_power_init(void)
 496 {
 497         struct exynos4_power *pwr =
 498                 (struct exynos4_power *)samsung_get_base_power();
 499
 500         /* PS HOLD */
 501         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 502
 503         /* Set power down */
 504         writel(0, (unsigned int)&pwr->cam_configuration);
 505         writel(0, (unsigned int)&pwr->tv_configuration);
 506         writel(0, (unsigned int)&pwr->mfc_configuration);
 507         writel(0, (unsigned int)&pwr->g3d_configuration);
 508         writel(0, (unsigned int)&pwr->lcd1_configuration);
 509         writel(0, (unsigned int)&pwr->gps_configuration);
 510         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 511
 512         /* It is necessary to power down core 1 */
 513         /* to successfully boot CPU1 in kernel */
 514         writel(0, (unsigned int)&pwr->arm_core1_configuration);
 515 }
 516
 517 static void exynos_uart_init(void)
 518 {
 519         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 520         gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
 521         gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
 522 }
 523
 524 int exynos_early_init_f(void)
 525 {
 526         wdt_stop();
 527         pmic_reset();
 528         board_clock_init();
 529         exynos_uart_init();
 530         board_power_init();
 531
 532         return 0;
 533 }
 534
 535 void exynos_reset_lcd(void)
 536 {
 537         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 538         udelay(10000);
 539         gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
 540         udelay(10000);
 541         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 542 }
 543
 544 int lcd_power(void)
 545 {
 546         int ret = 0;
 547         struct pmic *p = pmic_get("MAX8997_PMIC");
 548         if (!p)
 549                 return -ENODEV;
 550
 551         if (pmic_probe(p))
 552                 return 0;
 553
 554         /* LDO15 voltage: 2.2v */
 555         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 556         /* LDO13 voltage: 3.0v */
 557         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 558
 559         if (ret) {
 560                 puts("MAX8997 LDO setting error!\n");
 561                 return -1;
 562         }
 563
 564         return 0;
 565 }
 566
 567 int mipi_power(void)
 568 {
 569         int ret = 0;
 570         struct pmic *p = pmic_get("MAX8997_PMIC");
 571         if (!p)
 572                 return -ENODEV;
 573
 574         if (pmic_probe(p))
 575                 return 0;
 576
 577         /* LDO3 voltage: 1.1v */
 578         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 579         /* LDO4 voltage: 1.8v */
 580         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 581
 582         if (ret) {
 583                 puts("MAX8997 LDO setting error!\n");
 584                 return -1;
 585         }
 586
 587         return 0;
 588 }
 589
 590 void exynos_lcd_misc_init(vidinfo_t *vid)
 591 {
 592 #ifdef CONFIG_TIZEN
 593         get_tizen_logo_info(vid);
 594 #endif
 595 #ifdef CONFIG_S6E8AX0
 596         s6e8ax0_init();
 597         setenv("lcdinfo", "lcd=s6e8ax0");
 598 #endif
 599 }