2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/adc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/mmc.h>
33 #include <asm/arch/pinmux.h>
34 #include <asm/arch/watchdog.h>
37 #include <power/pmic.h>
38 #include <usb/s3c_udc.h>
39 #include <asm/arch/cpu.h>
40 #include <power/max8998_pmic.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 struct exynos4_gpio_part1 *gpio1;
45 struct exynos4_gpio_part2 *gpio2;
46 unsigned int board_rev;
48 u32 get_board_rev(void)
53 static int get_hwrev(void)
55 return board_rev & 0xFF;
58 int power_init_board(void)
62 ret = pmic_init(I2C_5);
71 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
72 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
77 void dram_init_banksize(void)
79 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
80 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
81 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
82 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
85 static unsigned short get_adc_value(int channel)
87 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
88 unsigned short ret = 0;
90 unsigned int loop = 0;
92 writel(channel & 0xF, &adc->adcmux);
93 writel((1 << 14) | (49 << 6), &adc->adccon);
94 writel(1000 & 0xffff, &adc->adcdly);
95 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
97 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
102 reg = readl(&adc->adccon);
103 } while (!(reg & (1 << 15)) && (loop++ < 1000));
105 ret = readl(&adc->adcdat0) & 0xFFF;
110 static int adc_power_control(int on)
113 struct pmic *p = pmic_get("MAX8998_PMIC");
120 ret = pmic_set_output(p,
127 static unsigned int get_hw_revision(void)
129 int hwrev, mode0, mode1;
131 adc_power_control(1);
133 mode0 = get_adc_value(1); /* HWREV_MODE0 */
134 mode1 = get_adc_value(2); /* HWREV_MODE1 */
137 * XXX Always set the default hwrev as the latest board
138 * ADC = (voltage) / 3.3 * 4096
142 #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
143 if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
144 hwrev = 0x0; /* 0.01V 0.01V */
145 if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
146 hwrev = 0x1; /* 610mV 0.01V */
147 if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
148 hwrev = 0x2; /* 1.16V 0.01V */
149 if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
150 hwrev = 0x3; /* 1.79V 0.01V */
153 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
155 adc_power_control(0);
160 static void check_hw_revision(void)
164 hwrev = get_hw_revision();
169 #ifdef CONFIG_DISPLAY_BOARDINFO
172 puts("Board:\tUniversal C210\n");
177 #ifdef CONFIG_GENERIC_MMC
178 int board_mmc_init(bd_t *bis)
182 switch (get_hwrev()) {
185 * Set the low to enable LDO_EN
186 * But when you use the test board for eMMC booting
187 * you should set it HIGH since it removes the inverter
189 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
190 s5p_gpio_direction_output(&gpio1->e3, 6, 0);
194 * Default reset state is High and there's no inverter
195 * But set it as HIGH to ensure
197 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
198 s5p_gpio_direction_output(&gpio1->e1, 3, 1);
204 * mmc0 : eMMC (8-bit buswidth)
205 * mmc2 : SD card (4-bit buswidth)
207 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
209 debug("SDMMC0 not configured\n");
211 err = s5p_mmc_init(0, 8);
214 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
215 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
218 * Check the T-flash detect pin
219 * GPX3[4] T-flash detect pin
221 if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
222 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
224 debug("SDMMC2 not configured\n");
226 err = s5p_mmc_init(2, 4);
234 #ifdef CONFIG_USB_GADGET
235 static int s5pc210_phy_control(int on)
238 struct pmic *p = pmic_get("MAX8998_PMIC");
246 ret |= pmic_set_output(p,
247 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
248 MAX8998_SAFEOUT1, LDO_ON);
249 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
250 MAX8998_LDO3, LDO_ON);
251 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
252 MAX8998_LDO8, LDO_ON);
255 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
256 MAX8998_LDO8, LDO_OFF);
257 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
258 MAX8998_LDO3, LDO_OFF);
259 ret |= pmic_set_output(p,
260 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
261 MAX8998_SAFEOUT1, LDO_OFF);
265 puts("MAX8998 LDO setting error!\n");
272 struct s3c_plat_otg_data s5pc210_otg_data = {
273 .phy_control = s5pc210_phy_control,
274 .regs_phy = EXYNOS4_USBPHY_BASE,
275 .regs_otg = EXYNOS4_USBOTG_BASE,
276 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
277 .usb_flags = PHY0_SLEEP,
281 int board_early_init_f(void)
288 #ifdef CONFIG_SOFT_SPI
289 static void soft_spi_init(void)
291 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
292 CONFIG_SOFT_SPI_MODE & SPI_CPOL);
293 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
294 gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
295 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
296 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
299 void spi_cs_activate(struct spi_slave *slave)
301 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
302 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
304 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
305 CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
308 void spi_cs_deactivate(struct spi_slave *slave)
310 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
311 !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
314 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
316 return bus == 0 && cs == 0;
319 void universal_spi_scl(int bit)
321 gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
324 void universal_spi_sda(int bit)
326 gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
329 int universal_spi_read(void)
331 return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
335 static void init_pmic_lcd(void)
340 struct pmic *p = get_pmic();
346 val = 0x02; /* (1800 - 1600) / 100; */
347 ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
350 val = 0xe; /* (3000 - 1600) / 100; */
351 ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
353 /* Disable unneeded regulators */
356 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
357 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
360 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
363 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
364 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
367 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
370 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
371 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
374 ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
377 puts("LCD pmic initialisation error!\n");
380 static void lcd_cfg_gpio(void)
382 unsigned int i, f3_end = 4;
384 for (i = 0; i < 8; i++) {
385 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
386 s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
387 s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
388 s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
389 /* pull-up/down disable */
390 s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
391 s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
392 s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
394 /* drive strength to max (24bit) */
395 s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
396 s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
397 s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
398 s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
399 s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
400 s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
403 for (i = 0; i < f3_end; i++) {
404 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
405 s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
406 /* pull-up/down disable */
407 s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
408 /* drive strength to max (24bit) */
409 s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
410 s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
413 /* gpio pad configuration for LCD reset. */
414 s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
419 static void reset_lcd(void)
421 s5p_gpio_set_value(&gpio2->y4, 5, 1);
423 s5p_gpio_set_value(&gpio2->y4, 5, 0);
425 s5p_gpio_set_value(&gpio2->y4, 5, 1);
429 static void lcd_power_on(void)
431 struct pmic *p = get_pmic();
436 pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
437 pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
440 vidinfo_t panel_info = {
446 .vl_clkp = CONFIG_SYS_HIGH,
447 .vl_hsp = CONFIG_SYS_HIGH,
448 .vl_vsp = CONFIG_SYS_HIGH,
449 .vl_dp = CONFIG_SYS_HIGH,
451 .vl_bpix = 5, /* Bits per pixel */
453 /* LD9040 LCD Panel */
461 .vl_cmd_allow_len = 0xf,
464 .cfg_gpio = lcd_cfg_gpio,
465 .backlight_on = NULL,
466 .lcd_power_on = lcd_power_on,
467 .reset_lcd = reset_lcd,
468 .dual_lcd_enabled = 0,
471 .power_on_delay = 10000,
472 .reset_delay = 10000,
473 .interface_mode = FIMD_RGB_INTERFACE,
477 void init_panel_info(vidinfo_t *vid)
480 vid->resolution = HD_RESOLUTION;
481 vid->rgb_mode = MODE_RGB_P;
484 get_tizen_logo_info(vid);
488 vid->pclk_name = 1; /* MPLL */
491 vid->cfg_ldo = ld9040_cfg_ldo;
492 vid->enable_ldo = ld9040_enable_ldo;
494 setenv("lcdinfo", "lcd=ld9040");
499 gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
500 gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
502 gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
503 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
505 #ifdef CONFIG_SOFT_SPI
509 printf("HW Revision:\t0x%x\n", board_rev);