2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/adc.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
31 #include <usb/s3c_udc.h>
32 #include <asm/arch/cpu.h>
33 #include <max8998_pmic.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 struct exynos4_gpio_part1 *gpio1;
38 struct exynos4_gpio_part2 *gpio2;
39 unsigned int board_rev;
41 u32 get_board_rev(void)
46 static int get_hwrev(void)
48 return board_rev & 0xFF;
51 static void check_hw_revision(void);
55 gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
56 gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
58 gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
59 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
61 #if defined(CONFIG_PMIC)
66 printf("HW Revision:\t0x%x\n", board_rev);
73 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
74 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
79 void dram_init_banksize(void)
81 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
82 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
83 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
84 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
87 static unsigned short get_adc_value(int channel)
89 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
90 unsigned short ret = 0;
92 unsigned int loop = 0;
94 writel(channel & 0xF, &adc->adcmux);
95 writel((1 << 14) | (49 << 6), &adc->adccon);
96 writel(1000 & 0xffff, &adc->adcdly);
97 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
99 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
104 reg = readl(&adc->adccon);
105 } while (!(reg & (1 << 15)) && (loop++ < 1000));
107 ret = readl(&adc->adcdat0) & 0xFFF;
112 static int adc_power_control(int on)
115 struct pmic *p = get_pmic();
120 ret = pmic_set_output(p,
127 static unsigned int get_hw_revision(void)
129 int hwrev, mode0, mode1;
131 adc_power_control(1);
133 mode0 = get_adc_value(1); /* HWREV_MODE0 */
134 mode1 = get_adc_value(2); /* HWREV_MODE1 */
137 * XXX Always set the default hwrev as the latest board
138 * ADC = (voltage) / 3.3 * 4096
142 #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
143 if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
144 hwrev = 0x0; /* 0.01V 0.01V */
145 if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
146 hwrev = 0x1; /* 610mV 0.01V */
147 if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
148 hwrev = 0x2; /* 1.16V 0.01V */
149 if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
150 hwrev = 0x3; /* 1.79V 0.01V */
153 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
155 adc_power_control(0);
160 static void check_hw_revision(void)
164 hwrev = get_hw_revision();
169 #ifdef CONFIG_DISPLAY_BOARDINFO
172 puts("Board:\tUniversal C210\n");
177 #ifdef CONFIG_GENERIC_MMC
178 int board_mmc_init(bd_t *bis)
182 switch (get_hwrev()) {
185 * Set the low to enable LDO_EN
186 * But when you use the test board for eMMC booting
187 * you should set it HIGH since it removes the inverter
189 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
190 s5p_gpio_direction_output(&gpio1->e3, 6, 0);
194 * Default reset state is High and there's no inverter
195 * But set it as HIGH to ensure
197 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
198 s5p_gpio_direction_output(&gpio1->e1, 3, 1);
204 * SDR 8-bit@48MHz at MMC0
205 * GPK0[0] SD_0_CLK(2)
206 * GPK0[1] SD_0_CMD(2)
207 * GPK0[2] SD_0_CDn -> Not used
208 * GPK0[3:6] SD_0_DATA[0:3](2)
209 * GPK1[3:6] SD_0_DATA[0:3](3)
211 * DDR 4-bit@26MHz at MMC4
212 * GPK0[0] SD_4_CLK(3)
213 * GPK0[1] SD_4_CMD(3)
214 * GPK0[2] SD_4_CDn -> Not used
215 * GPK0[3:6] SD_4_DATA[0:3](3)
216 * GPK1[3:6] SD_4_DATA[4:7](4)
218 for (i = 0; i < 7; i++) {
221 /* GPK0[0:6] special function 2 */
222 s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
223 /* GPK0[0:6] pull disable */
224 s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
225 /* GPK0[0:6] drv 4x */
226 s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
229 for (i = 3; i < 7; i++) {
230 /* GPK1[3:6] special function 3 */
231 s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
232 /* GPK1[3:6] pull disable */
233 s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
234 /* GPK1[3:6] drv 4x */
235 s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
239 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
240 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
244 * mmc0 : eMMC (8-bit buswidth)
245 * mmc2 : SD card (4-bit buswidth)
247 err = s5p_mmc_init(0, 8);
250 * Check the T-flash detect pin
251 * GPX3[4] T-flash detect pin
253 if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
256 * GPK2[0] SD_2_CLK(2)
257 * GPK2[1] SD_2_CMD(2)
258 * GPK2[2] SD_2_CDn -> Not used
259 * GPK2[3:6] SD_2_DATA[0:3](2)
261 for (i = 0; i < 7; i++) {
264 /* GPK2[0:6] special function 2 */
265 s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
266 /* GPK2[0:6] pull disable */
267 s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
268 /* GPK2[0:6] drv 4x */
269 s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
271 err = s5p_mmc_init(2, 4);
279 #ifdef CONFIG_USB_GADGET
280 static int s5pc210_phy_control(int on)
283 struct pmic *p = get_pmic();
289 ret |= pmic_set_output(p,
290 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
291 MAX8998_SAFEOUT1, LDO_ON);
292 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
293 MAX8998_LDO3, LDO_ON);
294 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
295 MAX8998_LDO8, LDO_ON);
298 ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
299 MAX8998_LDO8, LDO_OFF);
300 ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
301 MAX8998_LDO3, LDO_OFF);
302 ret |= pmic_set_output(p,
303 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
304 MAX8998_SAFEOUT1, LDO_OFF);
308 puts("MAX8998 LDO setting error!\n");
315 struct s3c_plat_otg_data s5pc210_otg_data = {
316 .phy_control = s5pc210_phy_control,
317 .regs_phy = EXYNOS4_USBPHY_BASE,
318 .regs_otg = EXYNOS4_USBOTG_BASE,
319 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
320 .usb_flags = PHY0_SLEEP,