3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "metrobox_version.h"
28 #include <timestamp.h>
29 #include <asm/processor.h>
31 #include <spd_sdram.h>
33 #include "../common/ppc440gx_i2c.h"
34 #include "../common/sb_common.h"
35 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
36 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
40 void fpga_init (void);
42 METROBOX_BOARD_ID_ST board_id_as[] =
43 { {"Undefined"}, /* Not specified */
44 {"2x10Gb"}, /* 2 ports, 10 GbE */
45 {"20x1Gb"}, /* 20 ports, 1 GbE */
46 {"Reserved"}, /* Reserved for future use */
49 /*************************************************************************
52 * Setup chip selects, initialize the Opto-FPGA, initialize
53 * interrupt polarity and triggers.
54 ************************************************************************/
55 int board_early_init_f (void)
57 ppc440_gpio_regs_t *gpio_regs;
59 /* Enable GPIO interrupts */
60 mtsdr(sdr_pfc0, 0x00103E00);
62 /* Setup access for LEDs, and system topology info */
63 gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
64 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
65 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
67 /* Turn on all the leds for now */
68 gpio_regs->out = SBCOMMON_GPIO_LEDS;
70 /*--------------------------------------------------------------------+
71 | Initialize EBC CONFIG
72 +-------------------------------------------------------------------*/
74 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
75 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
76 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
77 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
80 /*--------------------------------------------------------------------+
81 | 1/2 MB FLASH. Initialize bank 0 with default values.
82 +-------------------------------------------------------------------*/
84 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
85 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
86 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
87 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
88 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
89 EBC_BXAP_PEN_DISABLED);
91 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
92 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
93 /*--------------------------------------------------------------------+
94 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
95 +-------------------------------------------------------------------*/
97 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
98 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
99 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
100 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
101 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
102 EBC_BXAP_PEN_DISABLED);
104 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
105 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
107 /*--------------------------------------------------------------------+
108 | Compact Flash, uses 2 Chip Selects (2 & 6)
109 +-------------------------------------------------------------------*/
111 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
112 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
113 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
114 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
115 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
116 EBC_BXAP_PEN_DISABLED);
118 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
119 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
121 /*--------------------------------------------------------------------+
122 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
123 +-------------------------------------------------------------------*/
125 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
126 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
127 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
128 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
129 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
131 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
132 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
134 /*--------------------------------------------------------------------+
136 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
137 | Initialize bank 4 with default values.
138 +-------------------------------------------------------------------*/
140 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
141 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
142 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
143 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
144 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
146 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
147 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
149 /*--------------------------------------------------------------------+
150 | Metrobox MAC B Initialize bank 5 with default values.
151 | KA REF FPGA Initialize bank 5 with default values.
152 +-------------------------------------------------------------------*/
154 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
155 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
156 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
157 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
158 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
160 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
161 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
163 /*--------------------------------------------------------------------+
164 | Compact Flash, uses 2 Chip Selects (2 & 6)
165 +-------------------------------------------------------------------*/
167 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
168 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
169 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
170 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
171 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
172 EBC_BXAP_PEN_DISABLED);
174 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
175 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
177 /*--------------------------------------------------------------------+
178 | BME-32. Initialize bank 7 with default values.
179 +-------------------------------------------------------------------*/
181 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
182 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
183 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
184 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
185 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
187 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
188 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
190 /*--------------------------------------------------------------------+
191 * Setup the interrupt controller polarities, triggers, etc.
192 +-------------------------------------------------------------------*/
194 * Because of the interrupt handling rework to handle 440GX interrupts
195 * with the common code, we needed to change names of the UIC registers.
196 * Here the new relationship:
198 * U-Boot name 440GX name
199 * -----------------------
205 mtdcr (uic1sr, 0xffffffff); /* clear all */
206 mtdcr (uic1er, 0x00000000); /* disable all */
207 mtdcr (uic1cr, 0x00000000); /* all non- critical */
208 mtdcr (uic1pr, 0xfffffe03); /* polarity */
209 mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
210 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
211 mtdcr (uic1sr, 0xffffffff); /* clear all */
213 mtdcr (uic2sr, 0xffffffff); /* clear all */
214 mtdcr (uic2er, 0x00000000); /* disable all */
215 mtdcr (uic2cr, 0x00000000); /* all non-critical */
216 mtdcr (uic2pr, 0xffffc8ff); /* polarity */
217 mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
218 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
219 mtdcr (uic2sr, 0xffffffff); /* clear all */
221 mtdcr (uic3sr, 0xffffffff); /* clear all */
222 mtdcr (uic3er, 0x00000000); /* disable all */
223 mtdcr (uic3cr, 0x00000000); /* all non-critical */
224 mtdcr (uic3pr, 0xffff83ff); /* polarity */
225 mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
226 mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
227 mtdcr (uic3sr, 0xffffffff); /* clear all */
229 mtdcr (uic0sr, 0xfc000000); /* clear all */
230 mtdcr (uic0er, 0x00000000); /* disable all */
231 mtdcr (uic0cr, 0x00000000); /* all non-critical */
232 mtdcr (uic0pr, 0xfc000000);
233 mtdcr (uic0tr, 0x00000000);
234 mtdcr (uic0vr, 0x00000001);
241 /*************************************************************************
244 * Dump pertinent info to the console
245 ************************************************************************/
246 int checkboard (void)
249 unsigned char brd_rev, brd_id;
250 unsigned short sernum;
251 unsigned char opto_rev, opto_id;
252 OPTO_FPGA_REGS_ST *opto_ps;
254 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
256 opto_rev = (unsigned char)((opto_ps->revision_ul &
257 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
258 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
260 opto_id = (unsigned char)((opto_ps->revision_ul &
261 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
262 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
264 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
265 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
266 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
268 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
269 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
270 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
272 get_sys_info (&sysinfo);
274 sernum = sbcommon_get_serial_number();
275 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
276 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
278 printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
279 if (sbcommon_get_master()) {
280 printf("Slot 0 - Master\nSlave board");
281 if (sbcommon_secondary_present())
282 printf(" present\n");
284 printf(" not detected\n");
286 printf("Slot 1 - Slave\n\n");
289 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
290 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
292 /* Fix the ack in the bme 32 */
294 out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
301 /*************************************************************************
304 * Initialize I2C bus one to gain access to the fans
305 ************************************************************************/
306 int misc_init_f (void)
308 /* Turn on i2c bus 1 */
310 i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
319 /*************************************************************************
323 ************************************************************************/
324 int misc_init_r (void)
326 unsigned short sernum;
329 unsigned char opto_rev;
330 OPTO_FPGA_REGS_ST *opto_ps;
332 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
334 if(NULL != getenv("secondserial")) {
335 puts("secondserial is set, switching to second serial port\n");
336 setenv("stderr", "serial1");
337 setenv("stdout", "serial1");
338 setenv("stdin", "serial1");
341 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
343 memset(envstr, 0, 255);
344 sprintf (envstr, "Built %s %s by %s",
345 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
346 setenv("bldstr", envstr);
349 if( getenv("autorecover")) {
350 setenv("autorecover", NULL);
352 sernum = sbcommon_get_serial_number();
354 printf("\nSetting up environment for automatic filesystem recovery\n");
356 * Setup default bootargs
358 memset(envstr, 0, 255);
359 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
360 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
362 setenv("bootargs", envstr);
365 * Setup Default boot command
367 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
368 "fatload ide 0 8100000 pramdisk;"
369 "bootm 8000000 8100000");
371 printf("Done. Please type allow the system to continue to boot\n");
374 if( getenv("fakeled")) {
375 setenv("bootdelay", "-1");
377 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
378 opto_rev = (unsigned char)((opto_ps->revision_ul &
379 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
380 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
382 if(0x12 <= opto_rev) {
383 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
387 #ifdef CONFIG_HAS_ETH0
388 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
389 board_get_enetaddr(0, enetaddr);
390 eth_setenv_enetaddr("ethaddr", enetaddr);
394 #ifdef CONFIG_HAS_ETH1
395 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
396 board_get_enetaddr(1, enetaddr);
397 eth_setenv_enetaddr("eth1addr", enetaddr);
401 #ifdef CONFIG_HAS_ETH2
402 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
403 board_get_enetaddr(2, enetaddr);
404 eth_setenv_enetaddr("eth2addr", enetaddr);
408 #ifdef CONFIG_HAS_ETH3
409 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
410 board_get_enetaddr(3, enetaddr);
411 eth_setenv_enetaddr("eth3addr", enetaddr);
418 /*************************************************************************
420 ************************************************************************/
421 #ifdef CONFIG_IDE_RESET
422 void ide_set_reset(int on)
424 OPTO_FPGA_REGS_ST *opto_ps;
425 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
427 if (on) { /* assert RESET */
428 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
429 } else { /* release RESET */
430 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
433 #endif /* CONFIG_IDE_RESET */
435 /*************************************************************************
437 ************************************************************************/
440 OPTO_FPGA_REGS_ST *opto_ps;
441 unsigned char opto_rev;
444 /* Ensure we have power all around */
448 * Take appropriate hw bits out of reset
450 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
453 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
454 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
455 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
456 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
457 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
458 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
459 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
460 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
461 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
462 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
463 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
464 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
465 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
466 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
467 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
468 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
469 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
470 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
471 opto_ps->reset_ul = tmp;
473 * Turn on the 'Slow Blink' for the System Error Led.
474 * Ensure FPGA rev is up to at least rev 0x12
476 opto_rev = (unsigned char)((opto_ps->revision_ul &
477 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
478 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
479 if(0x12 <= opto_rev) {
480 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
488 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
490 unsigned short sernum;
493 sernum = sbcommon_get_serial_number();
495 memset(envstr, 0, 255);
497 * Setup our ip address
499 sprintf(envstr, "10.100.60.%d", sernum);
501 setenv("ipaddr", envstr);
503 * Setup the host ip address
505 setenv("serverip", "10.100.17.10");
508 * Setup default bootargs
510 memset(envstr, 0, 255);
512 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
513 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
514 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
515 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
516 sernum, sernum, sernum);
518 setenv("bootargs_nfs", envstr);
519 setenv("bootargs", envstr);
524 memset(envstr, 0, 255);
525 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
526 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
529 setenv("bootargs_cf", envstr);
532 * Setup Default boot command
534 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
535 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
538 * Setup compact flash boot command
540 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
548 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
550 unsigned short sernum;
553 sernum = sbcommon_get_serial_number();
555 printf("\nSetting up environment for filesystem recovery\n");
557 * Setup default bootargs
559 memset(envstr, 0, 255);
560 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
561 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
564 setenv("bootargs", envstr);
567 * Setup Default boot command
569 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
570 "fatload ide 0 8100000 pramdisk;"
571 "bootm 8000000 8100000");
573 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
574 " please type fsrecover.sh<cr>\n");
579 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
580 "Set environment to factory defaults", "");
582 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
583 "Set environment to allow for fs recovery", "");