3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "metrobox_version.h"
28 #include <asm/processor.h>
30 #include <spd_sdram.h>
32 #include "../common/ppc440gx_i2c.h"
33 #include "../common/sb_common.h"
37 void fpga_init (void);
39 METROBOX_BOARD_ID_ST board_id_as[] =
40 { {"Undefined"}, /* Not specified */
41 {"2x10Gb"}, /* 2 ports, 10 GbE */
42 {"20x1Gb"}, /* 20 ports, 1 GbE */
43 {"Reserved"}, /* Reserved for future use */
47 /*************************************************************************
50 * Setup chip selects, initialize the Opto-FPGA, initialize
51 * interrupt polarity and triggers.
53 ************************************************************************/
54 int board_early_init_f (void)
56 ppc440_gpio_regs_t *gpio_regs;
58 /* Enable GPIO interrupts */
59 mtsdr(sdr_pfc0, 0x00103E00);
61 /* Setup access for LEDs, and system topology info */
62 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
63 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
64 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
66 /* Turn on all the leds for now */
67 gpio_regs->out = SBCOMMON_GPIO_LEDS;
69 /*--------------------------------------------------------------------+
70 | Initialize EBC CONFIG
71 +-------------------------------------------------------------------*/
73 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
74 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
75 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
76 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
79 /*--------------------------------------------------------------------+
80 | 1/2 MB FLASH. Initialize bank 0 with default values.
81 +-------------------------------------------------------------------*/
83 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
84 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
85 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
86 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
87 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
88 EBC_BXAP_PEN_DISABLED);
90 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
91 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
92 /*--------------------------------------------------------------------+
93 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
94 +-------------------------------------------------------------------*/
96 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
97 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
98 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
99 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
100 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
101 EBC_BXAP_PEN_DISABLED);
103 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
104 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
106 /*--------------------------------------------------------------------+
107 | Compact Flash, uses 2 Chip Selects (2 & 6)
108 +-------------------------------------------------------------------*/
110 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
111 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
112 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
113 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
114 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
115 EBC_BXAP_PEN_DISABLED);
117 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
118 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
120 /*--------------------------------------------------------------------+
121 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
122 +-------------------------------------------------------------------*/
124 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
125 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
126 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
127 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
128 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
130 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
131 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
133 /*--------------------------------------------------------------------+
135 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
136 | Initialize bank 4 with default values.
137 +-------------------------------------------------------------------*/
139 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
140 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
141 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
142 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
143 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
145 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
146 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
148 /*--------------------------------------------------------------------+
149 | Metrobox MAC B Initialize bank 5 with default values.
150 | KA REF FPGA Initialize bank 5 with default values.
151 +-------------------------------------------------------------------*/
153 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
154 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
155 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
156 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
157 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
159 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
160 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
162 /*--------------------------------------------------------------------+
163 | Compact Flash, uses 2 Chip Selects (2 & 6)
164 +-------------------------------------------------------------------*/
166 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
167 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
168 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
169 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
170 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
171 EBC_BXAP_PEN_DISABLED);
173 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
174 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
176 /*--------------------------------------------------------------------+
177 | BME-32. Initialize bank 7 with default values.
178 +-------------------------------------------------------------------*/
180 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
181 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
182 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
183 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
184 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
186 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
187 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
190 /*--------------------------------------------------------------------+
191 * Setup the interrupt controller polarities, triggers, etc.
192 +-------------------------------------------------------------------*/
193 mtdcr (uic0sr, 0xffffffff); /* clear all */
194 mtdcr (uic0er, 0x00000000); /* disable all */
195 mtdcr (uic0cr, 0x00000000); /* all non- critical */
196 mtdcr (uic0pr, 0xfffffe03); /* polarity */
197 mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
198 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
199 mtdcr (uic0sr, 0xffffffff); /* clear all */
201 mtdcr (uic1sr, 0xffffffff); /* clear all */
202 mtdcr (uic1er, 0x00000000); /* disable all */
203 mtdcr (uic1cr, 0x00000000); /* all non-critical */
204 mtdcr (uic1pr, 0xffffc8ff); /* polarity */
205 mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
206 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
207 mtdcr (uic1sr, 0xffffffff); /* clear all */
209 mtdcr (uic2sr, 0xffffffff); /* clear all */
210 mtdcr (uic2er, 0x00000000); /* disable all */
211 mtdcr (uic2cr, 0x00000000); /* all non-critical */
212 mtdcr (uic2pr, 0xffff83ff); /* polarity */
213 mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
214 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
215 mtdcr (uic2sr, 0xffffffff); /* clear all */
217 mtdcr (uicb0sr, 0xfc000000); /* clear all */
218 mtdcr (uicb0er, 0x00000000); /* disable all */
219 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
220 mtdcr (uicb0pr, 0xfc000000);
221 mtdcr (uicb0tr, 0x00000000);
222 mtdcr (uicb0vr, 0x00000001);
230 /*************************************************************************
233 * Dump pertinent info to the console
235 ************************************************************************/
236 int checkboard (void)
239 unsigned char brd_rev, brd_id;
240 unsigned short sernum;
241 unsigned char opto_rev, opto_id;
242 OPTO_FPGA_REGS_ST *opto_ps;
244 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
246 opto_rev = (unsigned char)((opto_ps->revision_ul &
247 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
248 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
250 opto_id = (unsigned char)((opto_ps->revision_ul &
251 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
252 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
254 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
255 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
256 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
258 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
259 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
260 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
262 get_sys_info (&sysinfo);
264 sernum = sbcommon_get_serial_number();
265 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
266 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
268 printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
269 if (sbcommon_get_master()) {
270 printf("Slot 0 - Master\nSlave board");
271 if (sbcommon_secondary_present())
272 printf(" present\n");
274 printf(" not detected\n");
276 printf("Slot 1 - Slave\n\n");
279 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
280 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
282 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
283 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
284 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
285 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
286 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
289 /* Fix the ack in the bme 32 */
291 out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
299 /*************************************************************************
302 * Initialize I2C bus one to gain access to the fans
304 ************************************************************************/
305 int misc_init_f (void)
307 /* Turn on i2c bus 1 */
309 i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
317 /*************************************************************************
322 ************************************************************************/
323 int misc_init_r (void)
325 unsigned short sernum;
327 unsigned char opto_rev;
328 OPTO_FPGA_REGS_ST *opto_ps;
330 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
332 if(NULL != getenv("secondserial")) {
333 puts("secondserial is set, switching to second serial port\n");
334 setenv("stderr", "serial1");
335 setenv("stdout", "serial1");
336 setenv("stdin", "serial1");
339 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
341 memset(envstr, 0, 255);
342 sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
343 setenv("bldstr", envstr);
346 if( getenv("autorecover")) {
347 setenv("autorecover", NULL);
349 sernum = sbcommon_get_serial_number();
351 printf("\nSetting up environment for automatic filesystem recovery\n");
353 * Setup default bootargs
355 memset(envstr, 0, 255);
356 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
357 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
359 setenv("bootargs", envstr);
362 * Setup Default boot command
364 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
365 "fatload ide 0 8100000 pramdisk;"
366 "bootm 8000000 8100000");
368 printf("Done. Please type allow the system to continue to boot\n");
371 if( getenv("fakeled")) {
372 setenv("bootdelay", "-1");
374 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
375 opto_rev = (unsigned char)((opto_ps->revision_ul &
376 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
377 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
379 if(0x12 <= opto_rev) {
380 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
389 /*************************************************************************
394 ************************************************************************/
395 #ifdef CONFIG_IDE_RESET
396 void ide_set_reset(int on)
398 OPTO_FPGA_REGS_ST *opto_ps;
399 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
401 if (on) { /* assert RESET */
402 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
403 } else { /* release RESET */
404 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
407 #endif /* CONFIG_IDE_RESET */
409 /*************************************************************************
414 ************************************************************************/
417 OPTO_FPGA_REGS_ST *opto_ps;
418 unsigned char opto_rev;
421 /* Ensure we have power all around */
425 * Take appropriate hw bits out of reset
427 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
430 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
431 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
432 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
433 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
434 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
435 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
436 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
437 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
438 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
439 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
440 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
441 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
442 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
443 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
444 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
445 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
446 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
447 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
448 opto_ps->reset_ul = tmp;
450 * Turn on the 'Slow Blink' for the System Error Led.
451 * Ensure FPGA rev is up to at least rev 0x12
453 opto_rev = (unsigned char)((opto_ps->revision_ul &
454 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
455 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
456 if(0x12 <= opto_rev) {
457 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
467 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
469 unsigned short sernum;
472 sernum = sbcommon_get_serial_number();
474 memset(envstr, 0, 255);
476 * Setup our ip address
478 sprintf(envstr, "10.100.60.%d", sernum);
480 setenv("ipaddr", envstr);
482 * Setup the host ip address
484 setenv("serverip", "10.100.17.10");
487 * Setup default bootargs
489 memset(envstr, 0, 255);
491 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
492 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
493 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
494 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
495 sernum, sernum, sernum);
497 setenv("bootargs_nfs", envstr);
498 setenv("bootargs", envstr);
503 memset(envstr, 0, 255);
504 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
505 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
508 setenv("bootargs_cf", envstr);
511 * Setup Default boot command
513 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
514 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
517 * Setup compact flash boot command
519 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
528 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
530 unsigned short sernum;
533 sernum = sbcommon_get_serial_number();
535 printf("\nSetting up environment for filesystem recovery\n");
537 * Setup default bootargs
539 memset(envstr, 0, 255);
540 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
541 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
544 setenv("bootargs", envstr);
547 * Setup Default boot command
549 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
550 "fatload ide 0 8100000 pramdisk;"
551 "bootm 8000000 8100000");
553 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
554 " please type fsrecover.sh<cr>\n");
565 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
566 "mbsetup - Set environment to factory defaults\n", NULL);
568 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
569 "mbrecover - Set environment to allow for fs recovery\n", NULL);