3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "metrobox_version.h"
28 #include <timestamp.h>
29 #include <asm/processor.h>
31 #include <spd_sdram.h>
33 #include "../common/ppc440gx_i2c.h"
34 #include "../common/sb_common.h"
36 void fpga_init (void);
38 METROBOX_BOARD_ID_ST board_id_as[] =
39 { {"Undefined"}, /* Not specified */
40 {"2x10Gb"}, /* 2 ports, 10 GbE */
41 {"20x1Gb"}, /* 20 ports, 1 GbE */
42 {"Reserved"}, /* Reserved for future use */
45 /*************************************************************************
48 * Setup chip selects, initialize the Opto-FPGA, initialize
49 * interrupt polarity and triggers.
50 ************************************************************************/
51 int board_early_init_f (void)
53 ppc440_gpio_regs_t *gpio_regs;
55 /* Enable GPIO interrupts */
56 mtsdr(sdr_pfc0, 0x00103E00);
58 /* Setup access for LEDs, and system topology info */
59 gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
60 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
61 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
63 /* Turn on all the leds for now */
64 gpio_regs->out = SBCOMMON_GPIO_LEDS;
66 /*--------------------------------------------------------------------+
67 | Initialize EBC CONFIG
68 +-------------------------------------------------------------------*/
70 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
71 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
72 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
73 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
76 /*--------------------------------------------------------------------+
77 | 1/2 MB FLASH. Initialize bank 0 with default values.
78 +-------------------------------------------------------------------*/
80 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
81 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
82 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
83 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
84 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
85 EBC_BXAP_PEN_DISABLED);
87 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
88 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
89 /*--------------------------------------------------------------------+
90 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
91 +-------------------------------------------------------------------*/
93 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
94 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
95 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
96 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
97 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
98 EBC_BXAP_PEN_DISABLED);
100 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
101 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
103 /*--------------------------------------------------------------------+
104 | Compact Flash, uses 2 Chip Selects (2 & 6)
105 +-------------------------------------------------------------------*/
107 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
108 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
109 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
110 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
111 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
112 EBC_BXAP_PEN_DISABLED);
114 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
115 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
117 /*--------------------------------------------------------------------+
118 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
119 +-------------------------------------------------------------------*/
121 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
122 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
123 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
124 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
125 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
127 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
128 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
130 /*--------------------------------------------------------------------+
132 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
133 | Initialize bank 4 with default values.
134 +-------------------------------------------------------------------*/
136 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
137 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
138 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
139 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
140 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
142 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
143 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
145 /*--------------------------------------------------------------------+
146 | Metrobox MAC B Initialize bank 5 with default values.
147 | KA REF FPGA Initialize bank 5 with default values.
148 +-------------------------------------------------------------------*/
150 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
151 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
152 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
153 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
154 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
156 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
157 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
159 /*--------------------------------------------------------------------+
160 | Compact Flash, uses 2 Chip Selects (2 & 6)
161 +-------------------------------------------------------------------*/
163 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
164 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
165 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
166 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
167 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
168 EBC_BXAP_PEN_DISABLED);
170 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
171 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
173 /*--------------------------------------------------------------------+
174 | BME-32. Initialize bank 7 with default values.
175 +-------------------------------------------------------------------*/
177 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
178 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
179 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
180 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
181 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
183 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
184 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
186 /*--------------------------------------------------------------------+
187 * Setup the interrupt controller polarities, triggers, etc.
188 +-------------------------------------------------------------------*/
190 * Because of the interrupt handling rework to handle 440GX interrupts
191 * with the common code, we needed to change names of the UIC registers.
192 * Here the new relationship:
194 * U-Boot name 440GX name
195 * -----------------------
201 mtdcr (uic1sr, 0xffffffff); /* clear all */
202 mtdcr (uic1er, 0x00000000); /* disable all */
203 mtdcr (uic1cr, 0x00000000); /* all non- critical */
204 mtdcr (uic1pr, 0xfffffe03); /* polarity */
205 mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
206 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
207 mtdcr (uic1sr, 0xffffffff); /* clear all */
209 mtdcr (uic2sr, 0xffffffff); /* clear all */
210 mtdcr (uic2er, 0x00000000); /* disable all */
211 mtdcr (uic2cr, 0x00000000); /* all non-critical */
212 mtdcr (uic2pr, 0xffffc8ff); /* polarity */
213 mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
214 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
215 mtdcr (uic2sr, 0xffffffff); /* clear all */
217 mtdcr (uic3sr, 0xffffffff); /* clear all */
218 mtdcr (uic3er, 0x00000000); /* disable all */
219 mtdcr (uic3cr, 0x00000000); /* all non-critical */
220 mtdcr (uic3pr, 0xffff83ff); /* polarity */
221 mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
222 mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
223 mtdcr (uic3sr, 0xffffffff); /* clear all */
225 mtdcr (uic0sr, 0xfc000000); /* clear all */
226 mtdcr (uic0er, 0x00000000); /* disable all */
227 mtdcr (uic0cr, 0x00000000); /* all non-critical */
228 mtdcr (uic0pr, 0xfc000000);
229 mtdcr (uic0tr, 0x00000000);
230 mtdcr (uic0vr, 0x00000001);
237 /*************************************************************************
240 * Dump pertinent info to the console
241 ************************************************************************/
242 int checkboard (void)
245 unsigned char brd_rev, brd_id;
246 unsigned short sernum;
247 unsigned char opto_rev, opto_id;
248 OPTO_FPGA_REGS_ST *opto_ps;
250 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
252 opto_rev = (unsigned char)((opto_ps->revision_ul &
253 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
254 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
256 opto_id = (unsigned char)((opto_ps->revision_ul &
257 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
258 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
260 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
261 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
262 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
264 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
265 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
266 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
268 get_sys_info (&sysinfo);
270 sernum = sbcommon_get_serial_number();
271 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
272 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
274 printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
275 if (sbcommon_get_master()) {
276 printf("Slot 0 - Master\nSlave board");
277 if (sbcommon_secondary_present())
278 printf(" present\n");
280 printf(" not detected\n");
282 printf("Slot 1 - Slave\n\n");
285 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
286 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
288 /* Fix the ack in the bme 32 */
290 out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
297 /*************************************************************************
300 * Initialize I2C bus one to gain access to the fans
301 ************************************************************************/
302 int misc_init_f (void)
304 /* Turn on i2c bus 1 */
306 i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
315 /*************************************************************************
319 ************************************************************************/
320 int misc_init_r (void)
322 unsigned short sernum;
325 unsigned char opto_rev;
326 OPTO_FPGA_REGS_ST *opto_ps;
328 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
330 if(NULL != getenv("secondserial")) {
331 puts("secondserial is set, switching to second serial port\n");
332 setenv("stderr", "serial1");
333 setenv("stdout", "serial1");
334 setenv("stdin", "serial1");
337 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
339 memset(envstr, 0, 255);
340 sprintf (envstr, "Built %s %s by %s",
341 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
342 setenv("bldstr", envstr);
345 if( getenv("autorecover")) {
346 setenv("autorecover", NULL);
348 sernum = sbcommon_get_serial_number();
350 printf("\nSetting up environment for automatic filesystem recovery\n");
352 * Setup default bootargs
354 memset(envstr, 0, 255);
355 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
356 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
358 setenv("bootargs", envstr);
361 * Setup Default boot command
363 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
364 "fatload ide 0 8100000 pramdisk;"
365 "bootm 8000000 8100000");
367 printf("Done. Please type allow the system to continue to boot\n");
370 if( getenv("fakeled")) {
371 setenv("bootdelay", "-1");
373 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
374 opto_rev = (unsigned char)((opto_ps->revision_ul &
375 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
376 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
378 if(0x12 <= opto_rev) {
379 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
383 #ifdef CONFIG_HAS_ETH0
384 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
385 board_get_enetaddr(0, enetaddr);
386 eth_setenv_enetaddr("ethaddr", enetaddr);
390 #ifdef CONFIG_HAS_ETH1
391 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
392 board_get_enetaddr(1, enetaddr);
393 eth_setenv_enetaddr("eth1addr", enetaddr);
397 #ifdef CONFIG_HAS_ETH2
398 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
399 board_get_enetaddr(2, enetaddr);
400 eth_setenv_enetaddr("eth2addr", enetaddr);
404 #ifdef CONFIG_HAS_ETH3
405 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
406 board_get_enetaddr(3, enetaddr);
407 eth_setenv_enetaddr("eth3addr", enetaddr);
414 /*************************************************************************
416 ************************************************************************/
417 #ifdef CONFIG_IDE_RESET
418 void ide_set_reset(int on)
420 OPTO_FPGA_REGS_ST *opto_ps;
421 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
423 if (on) { /* assert RESET */
424 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
425 } else { /* release RESET */
426 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
429 #endif /* CONFIG_IDE_RESET */
431 /*************************************************************************
433 ************************************************************************/
436 OPTO_FPGA_REGS_ST *opto_ps;
437 unsigned char opto_rev;
440 /* Ensure we have power all around */
444 * Take appropriate hw bits out of reset
446 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
449 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
450 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
451 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
452 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
453 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
454 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
455 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
456 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
457 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
458 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
459 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
460 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
461 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
462 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
463 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
464 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
465 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
466 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
467 opto_ps->reset_ul = tmp;
469 * Turn on the 'Slow Blink' for the System Error Led.
470 * Ensure FPGA rev is up to at least rev 0x12
472 opto_rev = (unsigned char)((opto_ps->revision_ul &
473 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
474 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
475 if(0x12 <= opto_rev) {
476 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
484 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
486 unsigned short sernum;
489 sernum = sbcommon_get_serial_number();
491 memset(envstr, 0, 255);
493 * Setup our ip address
495 sprintf(envstr, "10.100.60.%d", sernum);
497 setenv("ipaddr", envstr);
499 * Setup the host ip address
501 setenv("serverip", "10.100.17.10");
504 * Setup default bootargs
506 memset(envstr, 0, 255);
508 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
509 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
510 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
511 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
512 sernum, sernum, sernum);
514 setenv("bootargs_nfs", envstr);
515 setenv("bootargs", envstr);
520 memset(envstr, 0, 255);
521 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
522 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
525 setenv("bootargs_cf", envstr);
528 * Setup Default boot command
530 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
531 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
534 * Setup compact flash boot command
536 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
544 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
546 unsigned short sernum;
549 sernum = sbcommon_get_serial_number();
551 printf("\nSetting up environment for filesystem recovery\n");
553 * Setup default bootargs
555 memset(envstr, 0, 255);
556 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
557 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
560 setenv("bootargs", envstr);
563 * Setup Default boot command
565 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
566 "fatload ide 0 8100000 pramdisk;"
567 "bootm 8000000 8100000");
569 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
570 " please type fsrecover.sh<cr>\n");
575 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
576 "Set environment to factory defaults", NULL);
578 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
579 "Set environment to allow for fs recovery", NULL);