2 * pci.c -- WindRiver SBC8349 PCI board support.
3 * Copyright (c) 2006 Wind River Systems, Inc.
5 * Based on MPC8349 PCI support but w/o PIB related code.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/global_data.h>
31 #include <asm/mpc8349_pci.h>
33 #if defined(CONFIG_OF_FLAT_TREE)
35 #elif defined(CONFIG_OF_LIBFDT)
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
44 /* System RAM mapped to PCI space */
45 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
46 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
48 #ifndef CONFIG_PCI_PNP
49 static struct pci_config_table pci_mpc8349emds_config_table[] = {
50 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
51 PCI_IDSEL_NUMBER, PCI_ANY_ID,
52 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
54 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
61 static struct pci_controller pci_hose[] = {
63 #ifndef CONFIG_PCI_PNP
64 config_table:pci_mpc8349emds_config_table,
68 #ifndef CONFIG_PCI_PNP
69 config_table:pci_mpc8349emds_config_table,
74 /**************************************************************************
77 * NOTICE: PCI2 is not supported. There is only one
78 * physical PCI slot on the board.
84 volatile immap_t * immr;
85 volatile clk83xx_t * clk;
86 volatile law83xx_t * pci_law;
87 volatile pot83xx_t * pci_pot;
88 volatile pcictrl83xx_t * pci_ctrl;
89 volatile pciconf83xx_t * pci_conf;
93 struct pci_controller * hose;
95 immr = (immap_t *)CFG_IMMR;
96 clk = (clk83xx_t *)&immr->clk;
97 pci_law = immr->sysconf.pcilaw;
98 pci_pot = immr->ios.pot;
99 pci_ctrl = immr->pci_ctrl;
100 pci_conf = immr->pci_conf;
105 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
110 clk->occr = 0xff000000;
114 * Release PCI RST Output signal
120 #ifdef CONFIG_MPC83XX_PCI2
126 /* We need to wait at least a 1sec based on PCI specs */
130 for (i = 0; i < 1000; ++i)
135 * Configure PCI Local Access Windows
137 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
138 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
140 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
141 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
144 * Configure PCI Outbound Translation Windows
147 /* PCI1 mem space - prefetch */
148 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
149 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
150 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
153 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
154 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
155 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
157 /* PCI1 mmio - non-prefetch mem space */
158 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
159 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
160 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
163 * Configure PCI Inbound Translation Windows
166 /* we need RAM mapped to PCI space for the devices to
167 * access main memory */
168 pci_ctrl[0].pitar1 = 0x0;
169 pci_ctrl[0].pibar1 = 0x0;
170 pci_ctrl[0].piebar1 = 0x0;
171 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
173 hose->first_busno = 0;
174 hose->last_busno = 0xff;
176 /* PCI memory prefetch space */
177 pci_set_region(hose->regions + 0,
181 PCI_REGION_MEM|PCI_REGION_PREFETCH);
183 /* PCI memory space */
184 pci_set_region(hose->regions + 1,
191 pci_set_region(hose->regions + 2,
197 /* System memory space */
198 pci_set_region(hose->regions + 3,
199 CONFIG_PCI_SYS_MEM_BUS,
200 CONFIG_PCI_SYS_MEM_PHYS,
202 PCI_REGION_MEM | PCI_REGION_MEMORY);
204 hose->region_count = 4;
206 pci_setup_indirect(hose,
210 pci_register_hose(hose);
213 * Write to Command register
216 dev = PCI_BDF(hose->first_busno, 0, 0);
217 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
218 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
219 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
222 * Clear non-reserved bits in status register.
224 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
225 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
226 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
228 #ifdef CONFIG_PCI_SCAN_SHOW
229 printf("PCI: Bus Dev VenId DevId Class Int\n");
234 hose->last_busno = pci_hose_scan(hose);
236 #ifdef CONFIG_MPC83XX_PCI2
240 * Configure PCI Outbound Translation Windows
243 /* PCI2 mem space - prefetch */
244 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
245 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
246 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
249 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
250 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
251 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
253 /* PCI2 mmio - non-prefetch mem space */
254 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
255 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
256 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
259 * Configure PCI Inbound Translation Windows
262 /* we need RAM mapped to PCI space for the devices to
263 * access main memory */
264 pci_ctrl[1].pitar1 = 0x0;
265 pci_ctrl[1].pibar1 = 0x0;
266 pci_ctrl[1].piebar1 = 0x0;
267 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
269 hose->first_busno = pci_hose[0].last_busno + 1;
270 hose->last_busno = 0xff;
272 /* PCI memory prefetch space */
273 pci_set_region(hose->regions + 0,
277 PCI_REGION_MEM|PCI_REGION_PREFETCH);
279 /* PCI memory space */
280 pci_set_region(hose->regions + 1,
287 pci_set_region(hose->regions + 2,
293 /* System memory space */
294 pci_set_region(hose->regions + 3,
295 CONFIG_PCI_SYS_MEM_BUS,
296 CONFIG_PCI_SYS_MEM_PHYS,
298 PCI_REGION_MEM | PCI_REGION_MEMORY);
300 hose->region_count = 4;
302 pci_setup_indirect(hose,
306 pci_register_hose(hose);
309 * Write to Command register
312 dev = PCI_BDF(hose->first_busno, 0, 0);
313 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
314 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
315 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
318 * Clear non-reserved bits in status register.
320 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
321 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
322 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
327 hose->last_busno = pci_hose_scan(hose);
332 #if defined(CONFIG_OF_LIBFDT)
333 void ft_pci_setup(void *blob, bd_t *bd)
339 nodeoffset = fdt_path_offset(blob, "/aliases");
340 if (nodeoffset >= 0) {
341 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
343 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
344 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
345 do_fixup_by_path(blob, path, "bus-range",
346 &tmp, sizeof(tmp), 1);
348 tmp[0] = cpu_to_be32(gd->pci_clk);
349 do_fixup_by_path(blob, path, "clock-frequency",
350 &tmp, sizeof(tmp[0]), 1);
352 #ifdef CONFIG_MPC83XX_PCI2
353 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
355 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
356 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
357 do_fixup_by_path(blob, path, "bus-range",
358 &tmp, sizeof(tmp), 1);
360 tmp[0] = cpu_to_be32(gd->pci_clk);
361 do_fixup_by_path(blob, path, "clock-frequency",
362 &tmp, sizeof(tmp[0]), 1);
367 #elif defined(CONFIG_OF_FLAT_TREE)
369 ft_pci_setup(void *blob, bd_t *bd)
374 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
376 p[0] = pci_hose[0].first_busno;
377 p[1] = pci_hose[0].last_busno;
380 #ifdef CONFIG_MPC83XX_PCI2
381 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
383 p[0] = pci_hose[1].first_busno;
384 p[1] = pci_hose[1].last_busno;
388 #endif /* CONFIG_OF_FLAT_TREE */
389 #endif /* CONFIG_PCI */