2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/mpc8349_pci.h>
35 #if defined(CONFIG_SPD_EEPROM)
36 #include <spd_sdram.h>
38 #if defined(CONFIG_OF_FLAT_TREE)
40 #elif defined(CONFIG_OF_LIBFDT)
44 int fixed_sdram(void);
45 void sdram_init(void);
47 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
48 void ddr_enable_ecc(unsigned int dram_size);
51 #ifdef CONFIG_BOARD_EARLY_INIT_F
52 int board_early_init_f (void)
58 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
60 long int initdram (int board_type)
62 volatile immap_t *im = (immap_t *)CFG_IMMR;
65 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
68 /* DDR SDRAM - Main SODIMM */
69 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
70 #if defined(CONFIG_SPD_EEPROM)
73 msize = fixed_sdram();
76 * Initialize SDRAM if it is on local bus.
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
82 * Initialize and enable DDR ECC.
84 ddr_enable_ecc(msize * 1024 * 1024);
86 /* return total bus SDRAM size(bytes) -- DDR */
87 return (msize * 1024 * 1024);
90 #if !defined(CONFIG_SPD_EEPROM)
91 /*************************************************************************
92 * fixed sdram init -- doesn't use serial presence detect.
93 ************************************************************************/
96 volatile immap_t *im = (immap_t *)CFG_IMMR;
101 msize = CFG_DDR_SIZE;
102 for (ddr_size = msize << 20, ddr_size_log2 = 0;
104 ddr_size = ddr_size>>1, ddr_size_log2++) {
109 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
110 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
112 #if (CFG_DDR_SIZE != 256)
113 #warning Currently any ddr size other than 256 is not supported
115 im->ddr.csbnds[2].csbnds = 0x0000000f;
116 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
118 /* currently we use only one CS, so disable the other banks */
119 im->ddr.cs_config[0] = 0;
120 im->ddr.cs_config[1] = 0;
121 im->ddr.cs_config[3] = 0;
123 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
124 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
128 #if defined(CONFIG_DDR_2T_TIMING)
131 | SDRAM_CFG_SDRAM_TYPE_DDR1;
132 #if defined (CONFIG_DDR_32BIT)
133 /* for 32-bit mode burst length is 8 */
134 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
136 im->ddr.sdram_mode = CFG_DDR_MODE;
138 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
141 /* enable DDR controller */
142 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
145 #endif/*!CFG_SPD_EEPROM*/
148 int checkboard (void)
150 puts("Board: Wind River SBC834x\n");
155 * if board is fitted with SDRAM
157 #if defined(CFG_BR2_PRELIM) \
158 && defined(CFG_OR2_PRELIM) \
159 && defined(CFG_LBLAWBAR2_PRELIM) \
160 && defined(CFG_LBLAWAR2_PRELIM)
162 * Initialize SDRAM memory on the Local Bus.
165 void sdram_init(void)
167 volatile immap_t *immap = (immap_t *)CFG_IMMR;
168 volatile lbus83xx_t *lbc= &immap->lbus;
169 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
171 puts("\n SDRAM on Local Bus: ");
172 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
175 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
178 /* setup mtrpt, lsrt and lbcr for LB bus */
179 lbc->lbcr = CFG_LBC_LBCR;
180 lbc->mrtpr = CFG_LBC_MRTPR;
181 lbc->lsrt = CFG_LBC_LSRT;
185 * Configure the SDRAM controller Machine Mode Register.
187 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
189 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
194 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
221 /* 0x58636733; mode register write operation */
222 lbc->lsdmr = CFG_LBC_LSDMR_4;
227 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
233 void sdram_init(void)
235 puts(" SDRAM on Local Bus: Disabled in config\n");
239 #if defined(CONFIG_OF_BOARD_SETUP)
240 void ft_board_setup(void *blob, bd_t *bd)
242 #if defined(CONFIG_OF_FLAT_TREE)
246 p = ft_get_prop(blob, "/memory/reg", &len);
248 *p++ = cpu_to_be32(bd->bi_memstart);
249 *p = cpu_to_be32(bd->bi_memsize);
252 ft_cpu_setup(blob, bd);
254 ft_pci_setup(blob, bd);