2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
40 #include <fdt_support.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 void local_bus_init(void);
45 void sdram_init(void);
46 long int fixed_sdram (void);
48 int board_early_init_f (void)
55 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
56 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
57 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
59 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
63 * Initialize local bus.
68 * Hack TSEC 3 and 4 IO voltages.
70 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
72 ecm->eedr = 0xffffffff; /* clear ecm errors */
73 ecm->eeer = 0xffffffff; /* enable ecm errors */
78 initdram(int board_type)
82 puts("Initializing\n");
84 #if defined(CONFIG_DDR_DLL)
87 * Work around to stabilize DDR DLL MSYNC_IN.
88 * Errata DDR9 seems to have been fixed.
89 * This is now the workaround for Errata DDR11:
90 * Override DLL = 1, Course Adj = 1, Tap Select = 0
93 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
95 gur->ddrdllcr = 0x81000000;
96 asm("sync;isync;msync");
101 #if defined(CONFIG_SPD_EEPROM)
102 dram_size = fsl_ddr_sdram();
103 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
104 dram_size *= 0x100000;
106 dram_size = fixed_sdram ();
110 * SDRAM Initialization
119 * Initialize Local Bus
124 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
125 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
131 get_sys_info(&sysinfo);
132 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
133 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
135 gur->lbiuiplldcr1 = 0x00078080;
137 gur->lbiuiplldcr0 = 0x7c0f1bf0;
138 } else if (clkdiv == 8) {
139 gur->lbiuiplldcr0 = 0x6c0f1bf0;
140 } else if (clkdiv == 4) {
141 gur->lbiuiplldcr0 = 0x5c0f1bf0;
144 lbc->lcrr |= 0x00030000;
146 asm("sync;isync;msync");
148 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
149 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
153 * Initialize SDRAM memory on the Local Bus.
158 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
161 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
162 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
167 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
170 * Setup SDRAM Base and Option Registers
172 lbc->or3 = CONFIG_SYS_OR3_PRELIM;
175 lbc->br3 = CONFIG_SYS_BR3_PRELIM;
178 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
182 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
183 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
187 * MPC8548 uses "new" 15-16 style addressing.
189 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
190 lsdmr_common |= LSDMR_BSMA1516;
193 * Issue PRECHARGE ALL command.
195 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
198 ppcDcbf((unsigned long) sdram_addr);
202 * Issue 8 AUTO REFRESH commands.
204 for (idx = 0; idx < 8; idx++) {
205 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
208 ppcDcbf((unsigned long) sdram_addr);
213 * Issue 8 MODE-set command.
215 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
218 ppcDcbf((unsigned long) sdram_addr);
222 * Issue NORMAL OP command.
224 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
227 ppcDcbf((unsigned long) sdram_addr);
228 udelay(200); /* Overkill. Must wait > 200 bus cycles */
230 #endif /* enable SDRAM init */
233 #if defined(CONFIG_SYS_DRAM_TEST)
237 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
238 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
241 printf("Testing DRAM from 0x%08x to 0x%08x\n",
242 CONFIG_SYS_MEMTEST_START,
243 CONFIG_SYS_MEMTEST_END);
245 printf("DRAM test phase 1:\n");
246 for (p = pstart; p < pend; p++)
249 for (p = pstart; p < pend; p++) {
250 if (*p != 0xaaaaaaaa) {
251 printf ("DRAM test fails at: %08x\n", (uint) p);
256 printf("DRAM test phase 2:\n");
257 for (p = pstart; p < pend; p++)
260 for (p = pstart; p < pend; p++) {
261 if (*p != 0x55555555) {
262 printf ("DRAM test fails at: %08x\n", (uint) p);
267 printf("DRAM test passed.\n");
272 #if !defined(CONFIG_SPD_EEPROM)
273 /*************************************************************************
274 * fixed_sdram init -- doesn't use serial presence detect.
275 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
276 ************************************************************************/
277 long int fixed_sdram (void)
279 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
281 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
283 ddr->cs0_bnds = 0x0000007f;
284 ddr->cs1_bnds = 0x008000ff;
285 ddr->cs2_bnds = 0x00000000;
286 ddr->cs3_bnds = 0x00000000;
287 ddr->cs0_config = 0x80010101;
288 ddr->cs1_config = 0x80010101;
289 ddr->cs2_config = 0x00000000;
290 ddr->cs3_config = 0x00000000;
291 ddr->timing_cfg_3 = 0x00000000;
292 ddr->timing_cfg_0 = 0x00220802;
293 ddr->timing_cfg_1 = 0x38377322;
294 ddr->timing_cfg_2 = 0x0fa044C7;
295 ddr->sdram_cfg = 0x4300C000;
296 ddr->sdram_cfg_2 = 0x24401000;
297 ddr->sdram_mode = 0x23C00542;
298 ddr->sdram_mode_2 = 0x00000000;
299 ddr->sdram_interval = 0x05080100;
300 ddr->sdram_md_cntl = 0x00000000;
301 ddr->sdram_data_init = 0x00000000;
302 ddr->sdram_clk_cntl = 0x03800000;
303 asm("sync;isync;msync");
306 #if defined (CONFIG_DDR_ECC)
307 /* Enable ECC checking */
308 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
310 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
313 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
318 static struct pci_controller pci1_hose;
319 #endif /* CONFIG_PCI1 */
322 static struct pci_controller pcie1_hose;
323 #endif /* CONFIG_PCIE1 */
325 int first_free_busno=0;
330 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
334 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
335 struct pci_controller *hose = &pci1_hose;
336 struct pci_region *r = hose->regions;
338 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
339 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
340 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
342 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
344 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
345 printf (" PCI host: %d bit, %s MHz, %s, %s\n",
347 (pci_speed == 33000000) ? "33" :
348 (pci_speed == 66000000) ? "66" : "unknown",
349 pci_clk_sel ? "sync" : "async",
350 pci_arb ? "arbiter" : "external-arbiter"
353 /* outbound memory */
355 CONFIG_SYS_PCI1_MEM_BASE,
356 CONFIG_SYS_PCI1_MEM_PHYS,
357 CONFIG_SYS_PCI1_MEM_SIZE,
362 CONFIG_SYS_PCI1_IO_BASE,
363 CONFIG_SYS_PCI1_IO_PHYS,
364 CONFIG_SYS_PCI1_IO_SIZE,
366 hose->region_count = r - hose->regions;
368 hose->first_busno=first_free_busno;
370 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
371 first_free_busno=hose->last_busno+1;
372 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
373 #ifdef CONFIG_PCIX_CHECK
374 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
376 if (CONFIG_SYS_CLK_FREQ < 66000000)
377 printf("PCI-X will only work at 66 MHz\n");
379 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
380 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
381 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
385 printf (" PCI: disabled\n");
389 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
392 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */
396 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
397 struct pci_controller *hose = &pcie1_hose;
398 struct pci_region *r = hose->regions;
400 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
402 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
403 printf ("\n PCIE at base address %x",
406 if (pci->pme_msg_det) {
407 pci->pme_msg_det = 0xffffffff;
408 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
412 /* outbound memory */
414 CONFIG_SYS_PCIE1_MEM_BASE,
415 CONFIG_SYS_PCIE1_MEM_PHYS,
416 CONFIG_SYS_PCIE1_MEM_SIZE,
421 CONFIG_SYS_PCIE1_IO_BASE,
422 CONFIG_SYS_PCIE1_IO_PHYS,
423 CONFIG_SYS_PCIE1_IO_SIZE,
426 hose->region_count = r - hose->regions;
428 hose->first_busno=first_free_busno;
430 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
431 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
433 first_free_busno=hose->last_busno+1;
436 printf (" PCIE: disabled\n");
440 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
445 int board_eth_init(bd_t *bis)
447 tsec_standard_init(bis);
449 return 0; /* otherwise cpu_eth_init gets run */
452 int last_stage_init(void)
457 #if defined(CONFIG_OF_BOARD_SETUP)
458 void ft_board_setup(void *blob, bd_t *bd)
460 ft_cpu_setup(blob, bd);
462 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
465 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);