4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/ic/sc520.h>
33 /* ------------------------------------------------------------------------- */
38 * We first set up all IRQs to be non-pci, edge triggered,
39 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
40 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
41 * as needed. Whe choose the irqs to gram from a configurable list
42 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
43 * such as 0 thngas will not work)
46 static void irq_init(void)
48 /* disable global interrupt mode */
49 write_mmcr_byte(SC520_PICICR, 0x40);
51 /* set all irqs to edge */
52 write_mmcr_byte(SC520_MPICMODE, 0x00);
53 write_mmcr_byte(SC520_SL1PICMODE, 0x00);
54 write_mmcr_byte(SC520_SL2PICMODE, 0x00);
56 /* active low polarity on PIC interrupt pins,
57 * active high polarity on all other irq pins */
58 write_mmcr_word(SC520_INTPINPOL, 0x0000);
60 /* set irq number mapping */
61 write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
62 write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
63 write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
64 write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
65 write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
66 write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
67 write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
68 write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
69 write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
70 write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
71 write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
72 write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/
73 write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
74 write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
75 write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
76 write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
77 write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
79 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
80 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
82 write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
83 write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */
84 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
85 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */
86 write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */
87 write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */
88 write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */
89 write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */
90 write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */
91 write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */
92 write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */
94 write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
95 write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
101 static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
103 int version = read_mmcr_byte(SC520_SYSINFO);
105 /* a configurable lists of irqs to steal
106 * when we need one (a board with more pci interrupt pins
107 * would use a larger table */
108 static int irq_list[] = {
114 static int next_irq_index=0;
119 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
122 pin-=1; /* pci config space use 1-based numbering */
124 return; /* device use no irq */
129 /* map device number + pin to a pin on the sc520 */
130 switch (PCI_DEV(dev)) {
143 case 9: /* PMC slot */
147 case 10: /* PC-Card */
160 pin&=3; /* wrap around */
162 if (sc520_pci_ints[pin] == -1) {
163 /* re-route one interrupt for us */
164 if (next_irq_index > 3) {
167 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
174 if (-1 != sc520_pci_ints[pin]) {
175 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
176 sc520_pci_ints[pin]);
179 printf("fixup_irq: device %d pin %c irq %d\n",
180 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
185 static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
186 pci_dev_t dev, struct pci_config_table *te)
191 pciauto_config_device(hose, dev);
193 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */
194 pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */
195 pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */
196 pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */
197 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */
198 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */
199 pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
201 pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */
202 pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */
203 /* route MF0 to ~INT and MF3 to IRQ7
204 * reserve all others */
205 pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
206 pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */
207 pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */
209 if (te->device != 0xac56) {
210 pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */
211 pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */
212 pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */
213 pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */
214 pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */
216 pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */
218 pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */
221 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
224 writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
225 writel(0, io_base+0x10); /* CLKRUN default */
226 writel(0, io_base+0x20); /* CLKRUN default */
232 static struct pci_config_table pci_sc520_spunk_config_table[] = {
233 { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
234 { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
235 { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
238 static struct pci_controller sc520_spunk_hose = {
239 fixup_irq: pci_sc520_spunk_fixup_irq,
240 config_table: pci_sc520_spunk_config_table,
245 void pci_init_board(void)
247 pci_sc520_init(&sc520_spunk_hose);
251 /* set up the ISA bus timing and system address mappings */
252 static void bus_init(void)
255 * 0 Hyglo versions 0.95 and 0.96 (large baords)
256 * ?? Hyglo version 0.97 (small board)
259 int version = read_mmcr_byte(SC520_SYSINFO);
262 /* set up the GP IO pins (for the Spunk board) */
263 write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */
264 write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */
265 write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */
266 write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */
267 write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */
268 write_mmcr_byte(SC520_CLKSEL, 0x70);
270 write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */
271 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
274 /* set up the GP IO pins (for the Hyglo board) */
275 write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */
276 write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */
277 write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */
278 write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */
279 write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */
280 write_mmcr_byte(SC520_CLKSEL, 0x70);
282 write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */
285 write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
286 write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
287 write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
288 write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
289 write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
290 write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
291 write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
293 write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */
295 /* adjust the memory map:
296 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
297 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
298 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
303 write_mmcr_long(SC520_PAR12, 0x8bffe800);
305 /* IDE0 = GPCS6 1f0-1f7 */
306 write_mmcr_long(SC520_PAR3, 0x380801f0);
308 /* IDE1 = GPCS7 3f6 */
309 write_mmcr_long(SC520_PAR4, 0x3c0003f6);
311 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
313 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
320 * PAR0 (legacy_video)
321 * PAR1 (PCI ROM mapping)
325 * PAR5 (legacy_video)
327 * PAR7 (legacy_video)
328 * PAR8 (legacy_video)
329 * PAR9 (legacy_video)
339 * This function should map a chunk of size bytes
340 * of the system address space to the ISA bus
342 * The function will return the memory address
343 * as seen by the host (which may very will be the
344 * same as the bus address)
346 u32 isa_map_rom(u32 bus_addr, int size)
350 printf("isa_map_rom asked to map %d bytes at %x\n",
361 par |= (bus_addr>>12);
364 printf ("setting PAR11 to %x\n", par);
366 /* Map rom 0x10000 with PAR1 */
367 write_mmcr_long(SC520_PAR11, par);
373 * this function removed any mapping created
374 * with pci_get_rom_window()
376 void isa_unmap_rom(u32 addr)
378 printf("isa_unmap_rom asked to unmap %x", addr);
379 if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
380 write_mmcr_long(SC520_PAR11, 0);
384 printf(" not ours\n");
388 #define PCI_ROM_TEMP_SPACE 0x10000
390 * This function should map a chunk of size bytes
391 * of the system address space to the PCI bus,
392 * suitable to map PCI ROMS (bus address < 16M)
393 * the function will return the host memory address
394 * which should be converted into a bus address
395 * before used to configure the PCI rom address
398 u32 pci_get_rom_window(struct pci_controller *hose, int size)
410 par |= (PCI_ROM_TEMP_SPACE>>16);
413 printf ("setting PAR1 to %x\n", par);
415 /* Map rom 0x10000 with PAR1 */
416 write_mmcr_long(SC520_PAR1, par);
418 return PCI_ROM_TEMP_SPACE;
422 * this function removed any mapping created
423 * with pci_get_rom_window()
425 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
427 printf("pci_remove_rom_window: %x", addr);
428 if (addr == PCI_ROM_TEMP_SPACE) {
429 write_mmcr_long(SC520_PAR1, 0);
433 printf(" not ours\n");
438 * This function is called in order to provide acces to the
439 * legacy video I/O ports on the PCI bus.
440 * After this function accesses to I/O ports 0x3b0-0x3bb and
441 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
444 int pci_enable_legacy_video_ports(struct pci_controller *hose)
446 /* Map video memory to 0xa0000*/
447 write_mmcr_long(SC520_PAR0, 0x7200400a);
449 /* forward all I/O accesses to PCI */
450 write_mmcr_byte(SC520_ADDDECCTL,
451 read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
454 /* so we map away all io ports to pci (only way to access pci io
455 * below 0x400. But then we have to map back the portions that we dont
456 * use so that the generate cycles on the GPIO bus where the sio and
457 * ISA slots are connected, this requre the use of several PAR registers
460 /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
461 write_mmcr_long(SC520_PAR5, 0x31f70100);
463 /* com2 use 2f8-2ff */
465 /* bring 0x300 - 0x3af back to ISA using PAR7 */
466 write_mmcr_long(SC520_PAR7, 0x30af0300);
468 /* vga use 3b0-3bb */
470 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
471 write_mmcr_long(SC520_PAR8, 0x300303bc);
473 /* vga use 3c0-3df */
475 /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
476 write_mmcr_long(SC520_PAR9, 0x301703e0);
478 /* com1 use 3f8-3ff */
485 * Miscelaneous platform dependent initialisations
490 DECLARE_GLOBAL_DATA_PTR;
496 /* max drive current on SDRAM */
497 write_mmcr_word(SC520_DSCTL, 0x0100);
499 /* enter debug mode after next reset (only if jumper is also set) */
500 write_mmcr_byte(SC520_RESCFG, 0x08);
501 /* configure the software timer to 33.000MHz */
502 write_mmcr_byte(SC520_SWTMRCFG, 1);
503 gd->bus_clk = 33000000;
514 void show_boot_progress(int val)
516 int version = read_mmcr_byte(SC520_SYSINFO);
519 /* PIO31-PIO16 Data */
520 write_mmcr_word(SC520_PIODATA31_16,
521 (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
523 /* PIO0-PIO15 Data */
524 write_mmcr_word(SC520_PIODATA15_0,
525 (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
527 /* newer boards use PIO4-PIO12 */
528 /* PIO0-PIO15 Data */
530 val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
532 val = (val & 0x007) | ((val & 0x07e) << 2);
534 write_mmcr_word(SC520_PIODATA15_0,
535 (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
540 int last_stage_init(void)
543 int version = read_mmcr_byte(SC520_SYSINFO);
545 printf("Omicron Ceti SC520 Spunk revision %x\n", version);
551 printf("eeprom probe %d\n", spi_eeprom_probe(1));
553 spi_eeprom_read(1, 0, (u8*)&x, 2);
554 spi_eeprom_read(1, 1, (u8*)&y, 2);
555 printf("eeprom bytes %04x%04x\n", x, y);
558 spi_eeprom_write(1, 0, (u8*)&x, 2);
559 spi_eeprom_write(1, 1, (u8*)&y, 2);
561 spi_eeprom_read(1, 0, (u8*)&x, 2);
562 spi_eeprom_read(1, 1, (u8*)&y, 2);
563 printf("eeprom bytes %04x%04x\n", x, y);
568 printf("eeprom probe %d\n", mw_eeprom_probe(1));
570 mw_eeprom_read(1, 0, (u8*)&x, 2);
571 mw_eeprom_read(1, 1, (u8*)&y, 2);
572 printf("eeprom bytes %04x%04x\n", x, y);
576 mw_eeprom_write(1, 0, (u8*)&x, 2);
577 mw_eeprom_write(1, 1, (u8*)&y, 2);
579 mw_eeprom_read(1, 0, (u8*)&x, 2);
580 mw_eeprom_read(1, 1, (u8*)&y, 2);
581 printf("eeprom bytes %04x%04x\n", x, y);
592 void ssi_chip_select(int dev)
594 int version = read_mmcr_byte(SC520_SYSINFO);
597 /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
600 write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
603 case 2: /* Temp Probe */
604 write_mmcr_word(SC520_PIOSET31_16, 0x0002);
608 write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
612 write_mmcr_word(SC520_PIOSET31_16, 0x0001);
616 write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
617 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
621 printf("Illegal SSI device requested: %d\n", dev);
625 /* Globox board: Both EEPROM and TEMP are active-high */
629 write_mmcr_word(SC520_PIOSET15_0, 0x0100);
632 case 2: /* Temp Probe */
633 write_mmcr_word(SC520_PIOSET15_0, 0x0080);
637 write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
641 printf("Illegal SSI device requested: %d\n", dev);
647 void spi_init_f(void)
649 read_mmcr_byte(SC520_SYSINFO) ?
650 spi_eeprom_probe(1) :
655 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
661 for (i=0;i<alen;i++) {
666 return read_mmcr_byte(SC520_SYSINFO) ?
667 spi_eeprom_read(1, offset, buffer, len) :
668 mw_eeprom_read(1, offset, buffer, len);
671 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
677 for (i=0;i<alen;i++) {
682 return read_mmcr_byte(SC520_SYSINFO) ?
683 spi_eeprom_write(1, offset, buffer, len) :
684 mw_eeprom_write(1, offset, buffer, len);