4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/ic/sc520.h>
31 #include <asm/ic/pci.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
37 int version = sc520_mmcr->sysinfo;
39 /* a configurable lists of irqs to steal
40 * when we need one (a board with more pci interrupt pins
41 * would use a larger table */
42 static int irq_list[] = {
43 CONFIG_SYS_FIRST_PCI_IRQ,
44 CONFIG_SYS_SECOND_PCI_IRQ,
45 CONFIG_SYS_THIRD_PCI_IRQ,
46 CONFIG_SYS_FORTH_PCI_IRQ
48 static int next_irq_index=0;
53 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
56 pin-=1; /* pci config space use 1-based numbering */
58 return; /* device use no irq */
62 /* map device number + pin to a pin on the sc520 */
63 switch (PCI_DEV(dev)) {
76 case 9: /* PMC slot */
80 case 10: /* PC-Card */
93 pin&=3; /* wrap around */
95 if (sc520_pci_ints[pin] == -1) {
96 /* re-route one interrupt for us */
97 if (next_irq_index > 3) {
100 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
107 if (-1 != sc520_pci_ints[pin]) {
108 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
109 sc520_pci_ints[pin]);
112 printf("fixup_irq: device %d pin %c irq %d\n",
113 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
118 static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
119 pci_dev_t dev, struct pci_config_table *te)
124 pciauto_config_device(hose, dev);
126 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */
127 pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */
128 pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */
129 pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */
130 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */
131 pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */
132 pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
134 pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */
135 pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */
136 /* route MF0 to ~INT and MF3 to IRQ7
137 * reserve all others */
138 pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
139 pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */
140 pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */
142 if (te->device != 0xac56) {
143 pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */
144 pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */
145 pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */
146 pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */
147 pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */
149 pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */
151 pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */
154 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
157 writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
158 writel(0, io_base+0x10); /* CLKRUN default */
159 writel(0, io_base+0x20); /* CLKRUN default */
164 static struct pci_config_table pci_sc520_spunk_config_table[] = {
165 { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
166 { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
167 { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
170 static struct pci_controller sc520_spunk_hose = {
171 fixup_irq: pci_sc520_spunk_fixup_irq,
172 config_table: pci_sc520_spunk_config_table,
177 void pci_init_board(void)
179 pci_sc520_init(&sc520_spunk_hose);
183 * This function should map a chunk of size bytes
184 * of the system address space to the ISA bus
186 * The function will return the memory address
187 * as seen by the host (which may very will be the
188 * same as the bus address)
190 u32 isa_map_rom(u32 bus_addr, int size)
194 printf("isa_map_rom asked to map %d bytes at %x\n",
205 par |= (bus_addr>>12);
208 printf ("setting PAR11 to %x\n", par);
210 /* Map rom 0x10000 with PAR1 */
211 sc520_mmcr->par[11] = par;
217 * this function removed any mapping created
218 * with pci_get_rom_window()
220 void isa_unmap_rom(u32 addr)
222 printf("isa_unmap_rom asked to unmap %x", addr);
223 if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
224 sc520_mmcr->par[11] = 0;
228 printf(" not ours\n");
231 #define PCI_ROM_TEMP_SPACE 0x10000
233 * This function should map a chunk of size bytes
234 * of the system address space to the PCI bus,
235 * suitable to map PCI ROMS (bus address < 16M)
236 * the function will return the host memory address
237 * which should be converted into a bus address
238 * before used to configure the PCI rom address
241 u32 pci_get_rom_window(struct pci_controller *hose, int size)
253 par |= (PCI_ROM_TEMP_SPACE>>16);
256 printf ("setting PAR1 to %x\n", par);
258 /* Map rom 0x10000 with PAR1 */
259 sc520_mmcr->par[1] = par;
261 return PCI_ROM_TEMP_SPACE;
265 * this function removed any mapping created
266 * with pci_get_rom_window()
268 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
270 printf("pci_remove_rom_window: %x", addr);
271 if (addr == PCI_ROM_TEMP_SPACE) {
272 sc520_mmcr->par[1] = 0;
276 printf(" not ours\n");
281 * This function is called in order to provide acces to the
282 * legacy video I/O ports on the PCI bus.
283 * After this function accesses to I/O ports 0x3b0-0x3bb and
284 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
287 int pci_enable_legacy_video_ports(struct pci_controller *hose)
289 /* Map video memory to 0xa0000*/
290 sc520_mmcr->par[0] = 0x7200400a;
292 /* forward all I/O accesses to PCI */
293 sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
296 /* so we map away all io ports to pci (only way to access pci io
297 * below 0x400. But then we have to map back the portions that we dont
298 * use so that the generate cycles on the GPIO bus where the sio and
299 * ISA slots are connected, this requre the use of several PAR registers
302 /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
303 sc520_mmcr->par[5] = 0x31f70100;
305 /* com2 use 2f8-2ff */
307 /* bring 0x300 - 0x3af back to ISA using PAR7 */
308 sc520_mmcr->par[7] = 0x30af0300;
310 /* vga use 3b0-3bb */
312 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
313 sc520_mmcr->par[8] = 0x300303bc;
315 /* vga use 3c0-3df */
317 /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
318 sc520_mmcr->par[9] = 0x301703e0;
320 /* com1 use 3f8-3ff */