5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* ------------------------------------------------------------------------- */
31 static long int dram_size (long int, long int *, long int);
33 /* ------------------------------------------------------------------------- */
35 /* used PLD registers */
36 # define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
37 # define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
38 # define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
39 # define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
40 # define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
42 #define _NOT_USED_ 0xFFFFFFFF
44 const uint sdram_table[] =
47 * Single Read. (Offset 0 in UPMA RAM)
49 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
52 * SDRAM Initialization (offset 5 in UPMA RAM)
54 * This is no UPM entry point. The following definition uses
55 * the remaining space to establish an initialization
56 * sequence, which is executed by a RUN command.
59 0xFFFAF834, 0xFFE5B435, /* last */
62 * Burst Read. (Offset 8 in UPMA RAM)
64 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
65 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 * Single Write. (Offset 18 in UPMA RAM)
72 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 * Burst Write. (Offset 20 in UPMA RAM)
78 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
79 0xF1AAF804, 0xFFA5F447, /* last */
80 _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 * Refresh (Offset 30 in UPMA RAM)
86 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
87 0xFFAFFC07, /* last */
88 _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 * MRS sequence (Offset 38 in UPMA RAM)
92 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
95 * Exception. (Offset 3c in UPMA RAM)
97 0xFFAFFC04, 0xFFAFFC05, /* last */
98 _NOT_USED_, _NOT_USED_,
101 /* ------------------------------------------------------------------------- */
105 long int initdram (int board_type)
107 volatile immap_t *immap = (immap_t *)CFG_IMMR;
108 volatile memctl8xx_t *memctl = &immap->im_memctl;
109 volatile iop8xx_t *iop = &immap->im_ioport;
110 volatile fec_t *fecp = &immap->im_cpm.cp_fec;
113 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
116 * Preliminary prescaler for refresh (depends on number of
117 * banks): This value is selected for four cycles every 62.4 us
118 * with two SDRAM banks or four cycles every 31.2 us with one
119 * bank. It will be adjusted after memory sizing.
121 memctl->memc_mptpr = CFG_MPTPR;
123 memctl->memc_mar = 0x00000088;
126 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
127 * preliminary addresses - these have to be modified after the
128 * SDRAM size has been determined.
130 memctl->memc_or2 = CFG_OR2_PRELIM;
131 memctl->memc_br2 = CFG_BR2_PRELIM;
133 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
137 /* perform SDRAM initializsation sequence */
139 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
141 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
144 memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
146 memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
148 memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
151 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
156 * Check Bank 0 Memory Size for re-configuration
159 size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
164 memctl->memc_mamr = CFG_MAMR;
170 memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
171 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
175 /* prepare pin multiplexing for fast ethernet */
178 fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
179 iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
185 /* ------------------------------------------------------------------------- */
188 * Check memory range for valid RAM. A simple memory test determines
189 * the actually available RAM size between addresses `base' and
190 * `base + maxsize'. Some (not all) hardware errors are detected:
191 * - short between address lines
192 * - short between data lines
195 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
197 volatile immap_t *immap = (immap_t *)CFG_IMMR;
198 volatile memctl8xx_t *memctl = &immap->im_memctl;
199 volatile long int *addr;
201 ulong save[32]; /* to make test non-destructive */
204 memctl->memc_mamr = mamr_value;
206 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
207 addr = base + cnt; /* pointer arith! */
213 /* write 0 to base address */
218 /* check at base address */
219 if ((val = *addr) != 0) {
224 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
225 addr = base + cnt; /* pointer arith! */
231 return (cnt * sizeof(long));
238 * Check Board Identity:
241 int checkboard (void)
246 void board_serial_init(void)
248 ;/* nothing to do here */
251 void board_ether_init(void)
253 volatile immap_t *immap = (immap_t *)CFG_IMMR;
254 volatile iop8xx_t *iop = &immap->im_ioport;
255 volatile fec_t *fecp = &immap->im_cpm.cp_fec;
258 fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
259 iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
262 int board_pre_init (void)
264 volatile immap_t *immap = (immap_t *)CFG_IMMR;
265 volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
266 volatile memctl8xx_t *memctl = &immap->im_memctl;
267 volatile iop8xx_t *iop = &immap->im_ioport;
269 /* configure the LED timing output pins - port A pin 4 */
270 iop->iop_papar = 0x0800;
271 iop->iop_padir = 0x0800;
273 /* start timer 2 for the 4hz LED blink rate */
274 timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
275 timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
276 timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
278 /* chip select for PLD access */
279 memctl->memc_br6 = 0x10000401;
280 memctl->memc_or6 = 0xFC000908;
282 /* PLD initial values ( set LEDs, remove reset on LXT) */
284 *PLD_GCR1_REG = 0x06;
286 *PLD_EXT_FETH = 0x40;
292 void board_get_enetaddr (uchar *addr)
295 volatile immap_t *immap = (immap_t *)CFG_IMMR;
296 volatile cpm8xx_t *cpm = &immap->im_cpm;
297 unsigned int rccrtmp;
299 char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
302 addr[i] = default_mac_addr[i];
304 printf("There is an error in the i2c driver .. /n");
305 printf("You need to fix it first....../n");
307 rccrtmp = cpm->cp_rccr;
308 cpm->cp_rccr |= 0x0020;
310 i2c_reg_read(0xa0, 0);
311 printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
312 i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
313 i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
315 cpm->cp_rccr = rccrtmp;