2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board
3 * (C) Copyright 2013 Siemens AG
6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
7 * (C) Copyright 2007-2008
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/at91sam9g45_matrix.h>
18 #include <asm/arch/at91sam9_smc.h>
19 #include <asm/arch/at91_common.h>
20 #include <asm/arch/at91_pmc.h>
21 #include <asm/arch/at91_rstc.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/clk.h>
25 #include <atmel_lcdc.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
32 DECLARE_GLOBAL_DATA_PTR;
34 static void corvus_nand_hw_init(void)
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 writel(csa, &matrix->ebicsa);
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
50 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_TDF_CYCLE(3),
64 at91_periph_clk_enable(ATMEL_ID_PIOC);
65 at91_periph_clk_enable(ATMEL_ID_PIOA);
67 /* Enable NandFlash */
68 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
72 #if defined(CONFIG_SPL_BUILD)
76 void at91_spl_board_init(void)
79 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
80 * mode, so it need do some action to exit mode.
82 at91_set_gpio_output(AT91_PIN_PD7, 0);
83 at91_set_gpio_output(AT91_PIN_PD8, 0);
84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
86 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
87 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
88 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
90 corvus_nand_hw_init();
92 /* Configure recovery button PINs */
93 at91_set_gpio_input(AT91_PIN_PB7, 1);
95 /* check if button is pressed */
96 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
99 debug("Recovery button pressed\n");
100 boot_device = spl_boot_device();
101 switch (boot_device) {
102 #ifdef CONFIG_SPL_NAND_SUPPORT
103 case BOOT_DEVICE_NAND:
105 spl_nand_erase_one(0, 0);
112 #include <asm/arch/atmel_mpddrc.h>
113 static void ddr2_conf(struct atmel_mpddr *ddr2)
115 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
117 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
118 ATMEL_MPDDRC_CR_NR_ROW_14 |
119 ATMEL_MPDDRC_CR_DIC_DS |
120 ATMEL_MPDDRC_CR_DQMS_SHARED |
121 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
124 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
125 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
126 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
127 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
128 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
129 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
130 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
131 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
133 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
134 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
135 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
136 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
138 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
139 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
140 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
141 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
146 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
147 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
148 struct atmel_mpddr ddr2;
153 /* enable DDR2 clock */
154 writel(0x4, &pmc->scer);
156 /* Chip select 1 is for DDR2/SDRAM */
157 csa = readl(&mat->ebicsa);
158 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
159 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
160 writel(csa, &mat->ebicsa);
162 /* DDRAM2 Controller initialize */
163 ddr2_init(ATMEL_BASE_CS6, &ddr2);
167 #ifdef CONFIG_CMD_USB
168 static void taurus_usb_hw_init(void)
170 at91_periph_clk_enable(ATMEL_ID_PIODE);
172 at91_set_gpio_output(AT91_PIN_PD1, 0);
173 at91_set_gpio_output(AT91_PIN_PD3, 0);
178 static void corvus_macb_hw_init(void)
181 at91_periph_clk_enable(ATMEL_ID_EMAC);
184 * Disable pull-up on:
185 * RXDV (PA15) => PHY normal mode (not Test mode)
186 * ERX0 (PA12) => PHY ADDR0
187 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
189 * PHY has internal pull-down
191 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
192 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
193 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
197 /* Re-enable pull-up */
198 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
199 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
200 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
207 int board_early_init_f(void)
209 at91_seriald_hw_init();
215 /* address of boot parameters */
216 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
218 #ifdef CONFIG_CMD_NAND
219 corvus_nand_hw_init();
221 #ifdef CONFIG_ATMEL_SPI
222 at91_spi0_hw_init(1 << 4);
224 #ifdef CONFIG_HAS_DATAFLASH
225 at91_spi0_hw_init(1 << 0);
228 corvus_macb_hw_init();
230 #ifdef CONFIG_CMD_USB
231 taurus_usb_hw_init();
238 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
239 CONFIG_SYS_SDRAM_SIZE);
243 int board_eth_init(bd_t *bis)
247 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
252 /* SPI chip select control */
253 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
255 return bus == 0 && cs < 2;
258 void spi_cs_activate(struct spi_slave *slave)
262 at91_set_gpio_output(AT91_PIN_PB18, 0);
266 at91_set_gpio_output(AT91_PIN_PB3, 0);
271 void spi_cs_deactivate(struct spi_slave *slave)
275 at91_set_gpio_output(AT91_PIN_PB18, 1);
279 at91_set_gpio_output(AT91_PIN_PB3, 1);