3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* ------------------------------------------------------------------------- */
33 static long int dram_size (long int, long int *, long int);
34 static void puma_status (void);
35 static void puma_set_mode (int mode);
36 static int puma_init_done (void);
37 static void puma_load (ulong addr, ulong len);
39 /* ------------------------------------------------------------------------- */
41 #define _NOT_USED_ 0xFFFFFFFF
44 * 50 MHz SDRAM access using UPM A
46 const uint sdram_table[] =
49 * Single Read. (Offset 0 in UPM RAM)
51 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
52 0x1ffddc47, /* last */
54 * SDRAM Initialization (offset 5 in UPM RAM)
56 * This is no UPM entry point. The following definition uses
57 * the remaining space to establish an initialization
58 * sequence, which is executed by a RUN command.
61 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
63 * Burst Read. (Offset 8 in UPM RAM)
65 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
66 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Single Write. (Offset 18 in UPM RAM)
73 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 * Burst Write. (Offset 20 in UPM RAM)
78 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
79 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 * Refresh (Offset 30 in UPM RAM)
86 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
87 0xfffffc84, 0xfffffc07, /* last */
88 _NOT_USED_, _NOT_USED_,
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
91 * Exception. (Offset 3c in UPM RAM)
93 0x7ffffc07, /* last */
94 _NOT_USED_, _NOT_USED_, _NOT_USED_,
97 /* ------------------------------------------------------------------------- */
100 * PUMA access using UPM B
102 const uint puma_table[] =
105 * Single Read. (Offset 0 in UPM RAM)
107 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 * Burst Read. (Offset 8 in UPM RAM)
116 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
121 * Single Write. (Offset 18 in UPM RAM)
123 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127 * Burst Write. (Offset 20 in UPM RAM)
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
132 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
134 * Refresh (Offset 30 in UPM RAM)
136 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
138 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
140 * Exception. (Offset 3c in UPM RAM)
142 0x7ffffc07, /* last */
143 _NOT_USED_, _NOT_USED_, _NOT_USED_,
146 /* ------------------------------------------------------------------------- */
150 * Check Board Identity:
154 int checkboard (void)
156 puts ("Board: Siemens PCU E\n");
160 /* ------------------------------------------------------------------------- */
163 initdram (int board_type)
165 volatile immap_t *immr = (immap_t *)CFG_IMMR;
166 volatile memctl8xx_t *memctl = &immr->im_memctl;
167 long int size_b0, reg;
171 * Configure UPMA for SDRAM
173 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
175 memctl->memc_mptpr = CFG_MPTPR;
177 /* burst length=4, burst type=sequential, CAS latency=2 */
178 memctl->memc_mar = 0x00000088;
181 * Map controller bank 2 to the SDRAM bank at preliminary address.
183 #if PCU_E_WITH_SWAPPED_CS /* XXX */
184 memctl->memc_or5 = CFG_OR5_PRELIM;
185 memctl->memc_br5 = CFG_BR5_PRELIM;
187 memctl->memc_or2 = CFG_OR2_PRELIM;
188 memctl->memc_br2 = CFG_BR2_PRELIM;
191 /* initialize memory address register */
192 memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
194 /* mode initialization (offset 5) */
195 #if PCU_E_WITH_SWAPPED_CS /* XXX */
196 udelay(200); /* 0x8000A105 */
197 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
199 udelay(200); /* 0x80004105 */
200 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
203 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
204 #if PCU_E_WITH_SWAPPED_CS /* XXX */
205 udelay(1); /* 0x8000A830 */
206 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
208 udelay(1); /* 0x80004830 */
209 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
212 #if PCU_E_WITH_SWAPPED_CS /* XXX */
213 udelay(1); /* 0x8000A106 */
214 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
216 udelay(1); /* 0x80004106 */
217 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
220 reg = memctl->memc_mamr;
221 reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
222 reg |= MAMR_TLFB_4X; /* ... to 4x */
223 reg |= MAMR_PTBE; /* enable refresh */
224 memctl->memc_mamr = reg;
228 /* Need at least 10 DRAM accesses to stabilize */
229 for (i=0; i<10; ++i) {
230 #if PCU_E_WITH_SWAPPED_CS /* XXX */
231 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
233 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
242 * Check Bank 0 Memory Size for re-configuration
244 #if PCU_E_WITH_SWAPPED_CS /* XXX */
245 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
247 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
250 memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
256 #if PCU_E_WITH_SWAPPED_CS /* XXX */
257 memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
258 memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
260 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
261 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
266 * Configure UPMB for PUMA
268 upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
273 /* ------------------------------------------------------------------------- */
276 * Check memory range for valid RAM. A simple memory test determines
277 * the actually available RAM size between addresses `base' and
278 * `base + maxsize'. Some (not all) hardware errors are detected:
279 * - short between address lines
280 * - short between data lines
283 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
285 volatile immap_t *immr = (immap_t *)CFG_IMMR;
286 volatile memctl8xx_t *memctl = &immr->im_memctl;
287 volatile long int *addr;
289 ulong save[32]; /* to make test non-destructive */
292 memctl->memc_mamr = mamr_value;
294 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
295 addr = base + cnt; /* pointer arith! */
301 /* write 0 to base address */
306 /* check at base address */
307 if ((val = *addr) != 0) {
312 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
313 addr = base + cnt; /* pointer arith! */
319 return (cnt * sizeof(long));
325 /* ------------------------------------------------------------------------- */
327 #if PCU_E_WITH_SWAPPED_CS /* XXX */
328 #define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
330 #define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
331 CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
334 #define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
338 immap_t *immr = (immap_t *)CFG_IMMR;
341 /* Configure all needed port pins for GPIO */
342 #if PCU_E_WITH_SWAPPED_CS /* XXX */
343 # if CFG_ETH_MDDIS_VALUE
344 immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
346 immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
348 immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
349 immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
350 immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
352 immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
353 immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
355 value = immr->im_cpm.cp_pbdat;
357 /* Assert Powerdown and Reset signals */
358 value |= CFG_PB_ETH_POWERDOWN;
359 value &= ~(CFG_PB_ETH_RESET);
361 /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
362 #if !PCU_E_WITH_SWAPPED_CS
363 # if CFG_ETH_MDDIS_VALUE
364 value |= CFG_PB_ETH_MDDIS;
366 value &= ~(CFG_PB_ETH_MDDIS);
369 #if CFG_ETH_CFG1_VALUE
370 value |= CFG_PB_ETH_CFG1;
372 value &= ~(CFG_PB_ETH_CFG1);
374 #if CFG_ETH_CFG2_VALUE
375 value |= CFG_PB_ETH_CFG2;
377 value &= ~(CFG_PB_ETH_CFG2);
379 #if CFG_ETH_CFG3_VALUE
380 value |= CFG_PB_ETH_CFG3;
382 value &= ~(CFG_PB_ETH_CFG3);
385 /* Drive output signals to initial state */
386 immr->im_cpm.cp_pbdat = value;
387 immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
390 /* De-assert Ethernet Powerdown */
391 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
394 /* de-assert RESET signal of PHY */
395 immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
399 /*-----------------------------------------------------------------------
400 * Board Special Commands: access functions for "PUMA" FPGA
402 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
404 #define PUMA_READ_MODE 0
405 #define PUMA_LOAD_MODE 1
407 int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
412 case 2: /* PUMA reset */
413 if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
418 case 4: /* PUMA load addr len */
419 if (strcmp(argv[1],"load") != 0)
422 addr = simple_strtoul(argv[2], NULL, 16);
423 len = simple_strtoul(argv[3], NULL, 16);
425 printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
427 puma_load (addr, len);
433 printf ("Usage:\n%s\n", cmdtp->usage);
436 cmd_tbl_t U_BOOT_CMD(puma) = MK_CMD_ENTRY(
437 "puma", 4, 1, do_puma,
438 "puma - access PUMA FPGA\n",
439 "status - print PUMA status\n"
440 "puma load addr len - load PUMA configuration data\n"
443 #endif /* CFG_CMD_BSP */
445 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
447 static void puma_set_mode (int mode)
449 volatile immap_t *immr = (immap_t *)CFG_IMMR;
450 volatile memctl8xx_t *memctl = &immr->im_memctl;
452 /* disable PUMA in memory controller */
453 #if PCU_E_WITH_SWAPPED_CS /* XXX */
454 memctl->memc_br3 = 0;
456 memctl->memc_br4 = 0;
461 #if PCU_E_WITH_SWAPPED_CS /* XXX */
462 memctl->memc_or3 = PUMA_CONF_OR_READ;
463 memctl->memc_br3 = PUMA_CONF_BR_READ;
465 memctl->memc_or4 = PUMA_CONF_OR_READ;
466 memctl->memc_br4 = PUMA_CONF_BR_READ;
470 #if PCU_E_WITH_SWAPPED_CS /* XXX */
471 memctl->memc_or3 = PUMA_CONF_OR_LOAD;
472 memctl->memc_br3 = PUMA_CONF_BR_LOAD;
474 memctl->memc_or4 = PUMA_CONF_OR_READ;
475 memctl->memc_br4 = PUMA_CONF_BR_READ;
481 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
483 #define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
485 static void puma_load (ulong addr, ulong len)
487 volatile immap_t *immr = (immap_t *)CFG_IMMR;
488 volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
489 uchar *data = (uchar *)addr;
497 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
498 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
499 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
501 #if PCU_E_WITH_SWAPPED_CS /* XXX */
502 immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
503 immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
504 immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
505 immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
507 immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
508 immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
509 immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
510 immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
514 #if PCU_E_WITH_SWAPPED_CS /* XXX */
515 immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
517 immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
520 /* wait until INIT indicates completion of reset */
521 for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
523 if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
526 if (i == PUMA_INIT_TIMEOUT) {
527 printf ("*** PUMA init timeout ***\n");
531 puma_set_mode (PUMA_LOAD_MODE);
534 *fpga_addr = *data++;
536 puma_set_mode (PUMA_READ_MODE);
541 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
543 static void puma_status (void)
546 printf ("PUMA initialization is %scomplete\n",
547 puma_init_done() ? "" : "NOT ");
550 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
552 static int puma_init_done (void)
554 volatile immap_t *immr = (immap_t *)CFG_IMMR;
556 /* make sure pin is GPIO input */
557 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
558 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
559 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
561 return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
564 /* ------------------------------------------------------------------------- */
566 int misc_init_r (void)
573 if (puma_init_done()) {
574 printf ("initialized\n");
578 if ((s = getenv("puma_addr")) != NULL)
579 addr = simple_strtoul(s, NULL, 16);
581 if ((s = getenv("puma_len")) != NULL)
582 len = simple_strtoul(s, NULL, 16);
584 if ((!addr) || (!len)) {
585 printf ("net list undefined\n");
589 printf ("loading... ");
591 puma_load (addr, len);
595 /* ------------------------------------------------------------------------- */