2 * (C) Copyright 2001, 2002
3 * Dave Ellis, SIXNET, dge@sixnetio.com.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * and other contributors to U-Boot. See file CREDITS for list
7 * of people who contributed to this project.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <jffs2/jffs2.h>
29 #include <net.h> /* for eth_init() */
32 #ifdef CONFIG_SHOW_BOOT_PROGRESS
33 # include <status_led.h>
36 #if defined(CONFIG_CMD_NAND)
37 #include <linux/mtd/nand_legacy.h>
38 extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
41 DECLARE_GLOBAL_DATA_PTR;
43 #define ORMASK(size) ((-size) & OR_AM_MSK)
45 static long ram_size(ulong *, long);
47 /* ------------------------------------------------------------------------- */
49 #ifdef CONFIG_SHOW_BOOT_PROGRESS
50 void show_boot_progress (int status)
52 #if defined(CONFIG_STATUS_LED)
53 # if defined(STATUS_LED_BOOT)
55 /* ready to transfer to kernel, make sure LED is proper state */
56 status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
58 # endif /* STATUS_LED_BOOT */
59 #endif /* CONFIG_STATUS_LED */
63 /* ------------------------------------------------------------------------- */
66 * Check Board Identity:
67 * returns 0 if recognized, -1 if unknown
72 puts ("Board: SIXNET SXNI855T\n");
76 /* ------------------------------------------------------------------------- */
78 #if defined(CONFIG_CMD_PCMCIA)
79 #error "SXNI855T has no PCMCIA port"
82 /* ------------------------------------------------------------------------- */
84 #define _not_used_ 0xffffffff
86 /* UPMB table for dual UART. */
88 /* this table is for 50MHz operation, it should work at all lower speeds */
89 const uint duart_table[] =
91 /* single read. (offset 0 in upm RAM) */
92 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
93 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
95 /* burst read. (offset 8 in upm RAM) */
96 _not_used_, _not_used_, _not_used_, _not_used_,
97 _not_used_, _not_used_, _not_used_, _not_used_,
98 _not_used_, _not_used_, _not_used_, _not_used_,
99 _not_used_, _not_used_, _not_used_, _not_used_,
101 /* single write. (offset 18 in upm RAM) */
102 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
103 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
105 /* burst write. (offset 20 in upm RAM) */
106 _not_used_, _not_used_, _not_used_, _not_used_,
107 _not_used_, _not_used_, _not_used_, _not_used_,
108 _not_used_, _not_used_, _not_used_, _not_used_,
109 _not_used_, _not_used_, _not_used_, _not_used_,
111 /* refresh. (offset 30 in upm RAM) */
112 _not_used_, _not_used_, _not_used_, _not_used_,
113 _not_used_, _not_used_, _not_used_, _not_used_,
114 _not_used_, _not_used_, _not_used_, _not_used_,
116 /* exception. (offset 3c in upm RAM) */
117 _not_used_, _not_used_, _not_used_, _not_used_,
120 /* Load FPGA very early in boot sequence, since it must be
121 * loaded before the 16C2550 serial channels can be used as
124 * Note: Much of the configuration is not complete. The
125 * stack is in DPRAM since SDRAM has not been initialized,
126 * so the stack must be kept small. Global variables
127 * are still in FLASH, so they cannot be written.
128 * Only the FLASH, DPRAM, immap and FPGA can be addressed,
129 * the other chip selects may not have been initialized.
130 * The clocks have been initialized, so udelay() can be
133 #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
134 #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
135 #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
136 #define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
138 int board_postclk_init (void)
141 /* the data to load to the XCSxxXL FPGA */
142 static const unsigned char fpgadata[] = {
143 # include "fpgadata.c"
146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
147 volatile memctl8xx_t *memctl = &immap->im_memctl;
148 #define porta (immap->im_ioport.iop_padat)
149 const unsigned char* pdata;
151 /* /INITFPGA and DONEFPGA signals are inputs */
152 immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
154 /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
155 porta &= ~FPGA_PROGRAM_L;
157 /* Set FPGA as an output */
158 immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
160 /* delay a little to make sure FPGA sees it, really
161 * only need less than a microsecond.
165 /* unassert /PROGRAM */
166 porta |= FPGA_PROGRAM_L;
168 /* delay while FPGA does last erase, indicated by
169 * /INITFPGA going high. This should happen within a
172 /* ### FIXME - a timeout check would be good, maybe flash
173 * the status LED to indicate the error?
175 while ((porta & FPGA_INIT_L) == 0)
178 /* write program data to FPGA at the programming address
179 * so extra /CS1 strobes at end of configuration don't actually
180 * write to any registers.
182 fpga = 0xff; /* first write is ignored */
183 fpga = 0xff; /* fill byte */
184 fpga = 0xff; /* fill byte */
185 fpga = 0x4f; /* preamble code */
186 fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
187 fpga = 0x4b; /* field check code */
190 /* while no error write out each of the 28 byte frames */
191 while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
192 && pdata < fpgadata + sizeof(fpgadata)) {
194 fpga = 0x4f; /* preamble code */
196 /* 21 bytes of data in a frame */
197 fpga = *(pdata++); fpga = *(pdata++);
198 fpga = *(pdata++); fpga = *(pdata++);
199 fpga = *(pdata++); fpga = *(pdata++);
200 fpga = *(pdata++); fpga = *(pdata++);
201 fpga = *(pdata++); fpga = *(pdata++);
202 fpga = *(pdata++); fpga = *(pdata++);
203 fpga = *(pdata++); fpga = *(pdata++);
204 fpga = *(pdata++); fpga = *(pdata++);
205 fpga = *(pdata++); fpga = *(pdata++);
206 fpga = *(pdata++); fpga = *(pdata++);
209 fpga = 0x4b; /* field check code */
210 fpga = 0xff; /* extended write cycle */
211 fpga = 0x4b; /* extended write cycle
212 * (actually 0x4b from bitgen.exe)
214 fpga = 0xff; /* extended write cycle */
215 fpga = 0xff; /* extended write cycle */
216 fpga = 0xff; /* extended write cycle */
219 fpga = 0xff; /* startup byte */
220 fpga = 0xff; /* startup byte */
221 fpga = 0xff; /* startup byte */
222 fpga = 0xff; /* startup byte */
224 #if 0 /* ### FIXME */
225 /* If didn't load all the data or FPGA_DONE is low the load failed.
226 * Maybe someday stop here and flash the status LED? The console
227 * is not configured, so can't print an error message. Can't write
228 * global variables to set a flag (except gd?).
229 * For now it must work.
233 /* Now that the FPGA is loaded, set up the Dual UART chip
234 * selects. Must be done here since it may be used as the console.
236 upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
238 memctl->memc_mbmr = DUART_MBMR;
239 memctl->memc_or5 = DUART_OR_VALUE;
240 memctl->memc_br5 = DUART_BR5_VALUE;
241 memctl->memc_or6 = DUART_OR_VALUE;
242 memctl->memc_br6 = DUART_BR6_VALUE;
247 /* ------------------------------------------------------------------------- */
249 /* base address for SRAM, assume 32-bit port, valid */
250 #define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
252 /* up to 64MB - will be adjusted for actual size */
253 #define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
254 | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
256 * Miscellaneous platform dependent initializations after running in RAM.
259 int misc_init_r (void)
261 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
262 volatile memctl8xx_t *memctl = &immap->im_memctl;
269 memctl->memc_or2 = NVRAM_OR_PRELIM;
270 memctl->memc_br2 = NVRAM_BR_VALUE;
272 /* Is there any SRAM? Is it 16 or 32 bits wide? */
274 /* First look for 32-bit SRAM */
275 bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
277 if (bd->bi_sramsize == 0) {
278 /* no 32-bit SRAM, but there could be 16-bit SRAM since
279 * it would report size 0 when configured for 32-bit bus.
280 * Try again with a 16-bit bus.
282 memctl->memc_br2 |= BR_PS_16;
283 bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
286 if (bd->bi_sramsize == 0) {
287 memctl->memc_br2 = 0; /* disable select since nothing there */
290 /* adjust or2 for actual size of SRAM */
291 memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
292 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
293 printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
297 /* set standard MPC8xx clock so kernel will see the time
298 * even if it doesn't have a DS1306 clock driver.
299 * This helps with experimenting with standard kernels.
305 rtc_get(&tmp); /* get time from DS1306 RTC */
307 /* convert to seconds since 1970 */
308 tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
309 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
311 immap->im_sitk.sitk_rtck = KAPWR_KEY;
312 immap->im_sit.sit_rtc = tim;
315 /* set up ethernet address for SCC ethernet. If eth1addr
316 * is present it gets a unique address, otherwise it
317 * shares the FEC address.
319 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
320 eth_getenv_enetaddr("ethaddr", enetaddr);
321 eth_setenv_enetaddr("eth1addr", enetaddr);
327 #if defined(CONFIG_CMD_NAND)
330 unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
332 printf ("%4lu MB\n", totlen >> 20);
336 /* ------------------------------------------------------------------------- */
339 * Check memory range for valid RAM. A simple memory test determines
340 * the actually available RAM size between addresses `base' and
343 * The memory size MUST be a power of 2 for this to work.
345 * The only memory modified is 8 bytes at offset 0. This is important
346 * since for the SRAM this location is reserved for autosizing, so if
347 * it is modified and the board is reset before ram_size() completes
348 * no damage is done. Normally even the memory at 0 is preserved. The
349 * higher SRAM addresses may contain battery backed RAM disk data which
350 * must never be corrupted.
353 static long ram_size(ulong *base, long maxsize)
355 volatile long *test_addr;
356 volatile ulong *base_addr = base;
357 ulong ofs; /* byte offset from base_addr */
358 ulong save; /* to make test non-destructive */
359 ulong save2; /* to make test non-destructive */
360 long ramsize = -1; /* size not determined yet */
362 save = *base_addr; /* save value at 0 so can restore */
363 save2 = *(base_addr+1); /* save value at 4 so can restore */
365 /* is any SRAM present? */
366 *base_addr = 0x5555aaaa;
368 /* It is important to drive the data bus with different data so
369 * it doesn't remember the value and look like RAM that isn't there.
371 *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
373 if (*base_addr != 0x5555aaaa)
374 ramsize = 0; /* no RAM present, or defective */
376 *base_addr = 0xaaaa5555;
377 *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
378 if (*base_addr != 0xaaaa5555)
379 ramsize = 0; /* no RAM present, or defective */
382 /* now size it if any is present */
383 for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
384 test_addr = (long*)((long)base_addr + ofs); /* location to test */
386 *base_addr = ~*test_addr;
387 if (*base_addr == *test_addr)
388 ramsize = ofs; /* wrapped back to 0, so this is the size */
391 *base_addr = save; /* restore value at 0 */
392 *(base_addr+1) = save2; /* restore value at 4 */
396 /* ------------------------------------------------------------------------- */
397 /* sdram table based on the FADS manual */
398 /* for chip MB811171622A-100 */
400 /* this table is for 50MHz operation, it should work at all lower speeds */
402 const uint sdram_table[] =
404 /* single read. (offset 0 in upm RAM) */
405 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
408 /* precharge and Mode Register Set initialization (offset 5).
409 * This is also entered at offset 6 to do Mode Register Set
410 * without the precharge.
412 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
414 /* burst read. (offset 8 in upm RAM) */
415 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
416 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
417 _not_used_, _not_used_, _not_used_, _not_used_,
418 _not_used_, _not_used_, _not_used_, _not_used_,
420 /* single write. (offset 18 in upm RAM) */
421 /* FADS had 0x1f27fc04, ...
422 * but most other boards have 0x1f07fc04, which
423 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
424 * like the single read.
425 * This seems better so I am going with the change.
427 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
428 _not_used_, _not_used_, _not_used_, _not_used_,
430 /* burst write. (offset 20 in upm RAM) */
431 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
432 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
433 _not_used_, _not_used_, _not_used_, _not_used_,
434 _not_used_, _not_used_, _not_used_, _not_used_,
436 /* refresh. (offset 30 in upm RAM) */
437 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
438 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
439 _not_used_, _not_used_, _not_used_, _not_used_,
441 /* exception. (offset 3c in upm RAM) */
442 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
444 /* ------------------------------------------------------------------------- */
446 #define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
448 /* precharge and set Mode Register */
449 #define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
450 MCR_MB_CS3 | /* chip select */ \
451 MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
453 /* set Mode Register, no precharge */
454 #define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
455 MCR_MB_CS3 | /* chip select */ \
456 MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
458 /* runs refresh loop twice so get 8 refresh cycles */
459 #define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
460 MCR_MB_CS3 | /* chip select */ \
461 MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
463 /* MAMR values work in either mamr or mbmr */
464 #define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
465 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
466 | MAMR_DSA_1_CYCL /* 1 cycle disable */ \
467 | MAMR_RLFA_1X /* Read loop 1 time */ \
468 | MAMR_WLFA_1X /* Write loop 1 time */ \
469 | MAMR_TLFA_4X) /* Timer loop 4 times */
471 #define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
472 | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
473 | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
476 #define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
477 | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
478 | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
480 /* base address 0, 32-bit port, SDRAM UPM, valid */
481 #define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
483 /* up to 256MB, SAM, G5LS - will be adjusted for actual size */
484 #define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
486 /* This is the Mode Select Register value for the SDRAM.
488 * Burst Type: sequential
490 * Write Burst Length: burst
492 #define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
494 /* ------------------------------------------------------------------------- */
496 phys_size_t initdram(int board_type)
498 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
499 volatile memctl8xx_t *memctl = &immap->im_memctl;
501 uint size_sdram9 = 0;
502 uint base = 0; /* SDRAM must start at 0 */
505 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
507 /* Configure the refresh (mostly). This needs to be
508 * based upon processor clock speed and optimized to provide
509 * the highest level of performance.
511 * Preliminary prescaler for refresh.
512 * This value is selected for four cycles in 31.2 us,
513 * which gives 8192 cycles in 64 milliseconds.
514 * This may be too fast, but works for any memory.
515 * It is adjusted to 4096 cycles in 64 milliseconds if
516 * possible once we know what memory we have.
518 * We have to be careful changing UPM registers after we
519 * ask it to run these commands.
521 * PTA - periodic timer period for our design is
523 * --------------- = 195
527 * 31.2us refresh interval
532 memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
533 memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
535 /* The SDRAM Mode Register value is shifted left 2 bits since
536 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
538 memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
539 udelay(200); /* SDRAM needs 200uS before set it up */
541 /* Now run the precharge/nop/mrs commands. */
542 memctl->memc_mcr = SDRAM_MCR_PRE;
545 /* Run 8 refresh cycles (2 sets of 4) */
546 memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
549 /* some brands want Mode Register set after the refresh
550 * cycles. This shouldn't hurt anything for the brands
551 * that were happy with the first time we set it.
553 memctl->memc_mcr = SDRAM_MCR_MRS;
556 memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
557 memctl->memc_or3 = SDRAM_OR_PRELIM;
558 memctl->memc_br3 = SDRAM_BR_VALUE + base;
560 /* Some brands need at least 10 DRAM accesses to stabilize.
561 * It wont hurt the brands that don't.
563 for (i=0; i<10; ++i) {
564 volatile ulong *addr = (volatile ulong *)base;
571 /* Check SDRAM memory Size in 8 column mode.
572 * For a 9 column memory we will get half the actual size.
574 size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
576 /* Check SDRAM memory Size in 9 column mode.
577 * For an 8 column memory we will see at most 4 megabytes.
579 memctl->memc_mamr = SDRAM_MAMR_9COL;
580 size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
582 if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
583 size_sdram = size_sdram9;
584 else /* go back to 8 columns */
585 memctl->memc_mamr = SDRAM_MAMR_8COL;
587 /* adjust or3 for actual size of SDRAM
589 memctl->memc_or3 |= ORMASK(size_sdram);
591 /* Adjust refresh rate depending on SDRAM type.
592 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
593 * it at the current (fast) rate.
594 * For 16, 64 and 128 MBit half the rate will do.
596 if (size_sdram <= 32 * 1024 * 1024)
597 memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */