git.sur5r.net Git - u-boot/blob - board/socrates/law.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2008
   4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5  *
   6  * Copyright 2008 Freescale Semiconductor, Inc.
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  */
  11
  12 #include <common.h>
  13 #include <asm/fsl_law.h>
  14 #include <asm/mmu.h>
  15
  16 /*
  17  * LAW(Local Access Window) configuration:
  18  *
  19  * 0x0000_0000     0x2fff_ffff     DDR                     512M
  20  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  21  * 0xc000_0000     0xc00f_ffff     FPGA                    1M
  22  * 0xc800_0000     0xcbff_ffff     LIME                    64M
  23  * 0xe000_0000     0xe00f_ffff     CCSR                    1M (mapped by CCSRBAR)
  24  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
  25  * 0xfc00_0000     0xffff_ffff     FLASH                   64M
  26  *
  27  * Notes:
  28  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  29  *    If flash is 8M at default position (last 8M), no LAW needed.
  30  */
  31
  32 struct law_entry law_table[] = {
  33         SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
  34         SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
  35         SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  36         SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
  37 #if defined(CONFIG_SYS_FPGA_BASE)
  38         SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
  39 #endif
  40         SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  41 };
  42
  43 int num_law_entries = ARRAY_SIZE(law_table);