4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
61 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
76 bool "sun5i (Allwinner A13)"
78 select ARM_CORTEX_CPU_IS_UP
79 select SUNXI_GEN_SUN4I
83 bool "sun6i (Allwinner A31)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun7i (Allwinner A20)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN4I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A23
103 bool "sun8i (Allwinner A23)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN6I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A33
113 bool "sun8i (Allwinner A33)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
122 config MACH_SUN8I_A83T
123 bool "sun8i (Allwinner A83T)"
125 select SUNXI_GEN_SUN6I
129 bool "sun8i (Allwinner H3)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select MACH_SUNXI_H3_H5
135 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
137 config MACH_SUN8I_R40
138 bool "sun8i (Allwinner R40)"
140 select SUNXI_GEN_SUN6I
143 bool "sun9i (Allwinner A80)"
145 select SUNXI_HIGH_SRAM
146 select SUNXI_GEN_SUN6I
150 bool "sun50i (Allwinner A64)"
152 select SUNXI_GEN_SUN6I
153 select SUNXI_HIGH_SRAM
156 config MACH_SUN50I_H5
157 bool "sun50i (Allwinner H5)"
159 select MACH_SUNXI_H3_H5
160 select SUNXI_HIGH_SRAM
164 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
167 default y if MACH_SUN8I_A23
168 default y if MACH_SUN8I_A33
169 default y if MACH_SUN8I_A83T
170 default y if MACH_SUNXI_H3_H5
171 default y if MACH_SUN8I_R40
173 config RESERVE_ALLWINNER_BOOT0_HEADER
174 bool "reserve space for Allwinner boot0 header"
175 select ENABLE_ARM_SOC_BOOT0_HOOK
177 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
178 filled with magic values post build. The Allwinner provided boot0
179 blob relies on this information to load and execute U-Boot.
180 Only needed on 64-bit Allwinner boards so far when using boot0.
182 config ARM_BOOT_HOOK_RMR
186 select ENABLE_ARM_SOC_BOOT0_HOOK
188 Insert some ARM32 code at the very beginning of the U-Boot binary
189 which uses an RMR register write to bring the core into AArch64 mode.
190 The very first instruction acts as a switch, since it's carefully
191 chosen to be a NOP in one mode and a branch in the other, so the
192 code would only be executed if not already in AArch64.
193 This allows both the SPL and the U-Boot proper to be entered in
194 either mode and switch to AArch64 if needed.
197 int "sunxi dram type"
198 depends on MACH_SUN8I_A83T
201 Set the dram type, 3: DDR3, 7: LPDDR3
204 int "sunxi dram clock speed"
205 default 792 if MACH_SUN9I
206 default 648 if MACH_SUN8I_R40
207 default 312 if MACH_SUN6I || MACH_SUN8I
208 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
209 default 672 if MACH_SUN50I
211 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
212 must be a multiple of 24. For the sun9i (A80), the tested values
213 (for DDR3-1600) are 312 to 792.
215 if MACH_SUN5I || MACH_SUN7I
217 int "sunxi mbus clock speed"
220 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
225 int "sunxi dram zq value"
226 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
227 default 127 if MACH_SUN7I
228 default 3881979 if MACH_SUN8I_R40
229 default 4145117 if MACH_SUN9I
230 default 3881915 if MACH_SUN50I
232 Set the dram zq value.
235 bool "sunxi dram odt enable"
236 default n if !MACH_SUN8I_A23
237 default y if MACH_SUN8I_A23
238 default y if MACH_SUN8I_R40
239 default y if MACH_SUN50I
241 Select this to enable dram odt (on die termination).
243 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
245 int "sunxi dram emr1 value"
246 default 0 if MACH_SUN4I
247 default 4 if MACH_SUN5I || MACH_SUN7I
249 Set the dram controller emr1 value.
252 hex "sunxi dram tpr3 value"
255 Set the dram controller tpr3 parameter. This parameter configures
256 the delay on the command lane and also phase shifts, which are
257 applied for sampling incoming read data. The default value 0
258 means that no phase/delay adjustments are necessary. Properly
259 configuring this parameter increases reliability at high DRAM
262 config DRAM_DQS_GATING_DELAY
263 hex "sunxi dram dqs_gating_delay value"
266 Set the dram controller dqs_gating_delay parmeter. Each byte
267 encodes the DQS gating delay for each byte lane. The delay
268 granularity is 1/4 cycle. For example, the value 0x05060606
269 means that the delay is 5 quarter-cycles for one lane (1.25
270 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
271 The default value 0 means autodetection. The results of hardware
272 autodetection are not very reliable and depend on the chip
273 temperature (sometimes producing different results on cold start
274 and warm reboot). But the accuracy of hardware autodetection
275 is usually good enough, unless running at really high DRAM
276 clocks speeds (up to 600MHz). If unsure, keep as 0.
279 prompt "sunxi dram timings"
280 default DRAM_TIMINGS_VENDOR_MAGIC
282 Select the timings of the DDR3 chips.
284 config DRAM_TIMINGS_VENDOR_MAGIC
285 bool "Magic vendor timings from Android"
287 The same DRAM timings as in the Allwinner boot0 bootloader.
289 config DRAM_TIMINGS_DDR3_1066F_1333H
290 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
292 Use the timings of the standard JEDEC DDR3-1066F speed bin for
293 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
294 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
295 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
296 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
297 that down binning to DDR3-1066F is supported (because DDR3-1066F
298 uses a bit faster timings than DDR3-1333H).
300 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
301 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
303 Use the timings of the slowest possible JEDEC speed bin for the
304 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
305 DDR3-800E, DDR3-1066G or DDR3-1333J.
312 config DRAM_ODT_CORRECTION
313 int "sunxi dram odt correction value"
316 Set the dram odt correction value (range -255 - 255). In allwinner
317 fex files, this option is found in bits 8-15 of the u32 odt_en variable
318 in the [dram] section. When bit 31 of the odt_en variable is set
319 then the correction is negative. Usually the value for this is 0.
323 default 1008000000 if MACH_SUN4I
324 default 1008000000 if MACH_SUN5I
325 default 1008000000 if MACH_SUN6I
326 default 912000000 if MACH_SUN7I
327 default 1008000000 if MACH_SUN8I
328 default 1008000000 if MACH_SUN9I
329 default 816000000 if MACH_SUN50I
331 config SYS_CONFIG_NAME
332 default "sun4i" if MACH_SUN4I
333 default "sun5i" if MACH_SUN5I
334 default "sun6i" if MACH_SUN6I
335 default "sun7i" if MACH_SUN7I
336 default "sun8i" if MACH_SUN8I
337 default "sun9i" if MACH_SUN9I
338 default "sun50i" if MACH_SUN50I
347 bool "UART0 on MicroSD breakout board"
350 Repurpose the SD card slot for getting access to the UART0 serial
351 console. Primarily useful only for low level u-boot debugging on
352 tablets, where normal UART0 is difficult to access and requires
353 device disassembly and/or soldering. As the SD card can't be used
354 at the same time, the system can be only booted in the FEL mode.
355 Only enable this if you really know what you are doing.
357 config OLD_SUNXI_KERNEL_COMPAT
358 bool "Enable workarounds for booting old kernels"
361 Set this to enable various workarounds for old kernels, this results in
362 sub-optimal settings for newer kernels, only enable if needed.
365 string "MAC power pin"
368 Set the pin used to power the MAC. This takes a string in the format
369 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
372 string "Card detect pin for mmc0"
373 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
376 Set the card detect pin for mmc0, leave empty to not use cd. This
377 takes a string in the format understood by sunxi_name_to_gpio, e.g.
378 PH1 for pin 1 of port H.
381 string "Card detect pin for mmc1"
384 See MMC0_CD_PIN help text.
387 string "Card detect pin for mmc2"
390 See MMC0_CD_PIN help text.
393 string "Card detect pin for mmc3"
396 See MMC0_CD_PIN help text.
399 string "Pins for mmc1"
402 Set the pins used for mmc1, when applicable. This takes a string in the
403 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
406 string "Pins for mmc2"
409 See MMC1_PINS help text.
412 string "Pins for mmc3"
415 See MMC1_PINS help text.
417 config MMC_SUNXI_SLOT_EXTRA
418 int "mmc extra slot number"
421 sunxi builds always enable mmc0, some boards also have a second sdcard
422 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
425 config INITIAL_USB_SCAN_DELAY
426 int "delay initial usb scan by x ms to allow builtin devices to init"
429 Some boards have on board usb devices which need longer than the
430 USB spec's 1 second to connect from board powerup. Set this config
431 option to a non 0 value to add an extra delay before the first usb
435 string "Vbus enable pin for usb0 (otg)"
438 Set the Vbus enable pin for usb0 (otg). This takes a string in the
439 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
442 string "Vbus detect pin for usb0 (otg)"
445 Set the Vbus detect pin for usb0 (otg). This takes a string in the
446 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
449 string "ID detect pin for usb0 (otg)"
452 Set the ID detect pin for usb0 (otg). This takes a string in the
453 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
456 string "Vbus enable pin for usb1 (ehci0)"
457 default "PH6" if MACH_SUN4I || MACH_SUN7I
458 default "PH27" if MACH_SUN6I
460 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
461 a string in the format understood by sunxi_name_to_gpio, e.g.
462 PH1 for pin 1 of port H.
465 string "Vbus enable pin for usb2 (ehci1)"
466 default "PH3" if MACH_SUN4I || MACH_SUN7I
467 default "PH24" if MACH_SUN6I
469 See USB1_VBUS_PIN help text.
472 string "Vbus enable pin for usb3 (ehci2)"
475 See USB1_VBUS_PIN help text.
478 bool "Enable I2C/TWI controller 0"
479 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
480 default n if MACH_SUN6I || MACH_SUN8I
483 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
484 its clock and setting up the bus. This is especially useful on devices
485 with slaves connected to the bus or with pins exposed through e.g. an
486 expansion port/header.
489 bool "Enable I2C/TWI controller 1"
493 See I2C0_ENABLE help text.
496 bool "Enable I2C/TWI controller 2"
500 See I2C0_ENABLE help text.
502 if MACH_SUN6I || MACH_SUN7I
504 bool "Enable I2C/TWI controller 3"
508 See I2C0_ENABLE help text.
513 bool "Enable the PRCM I2C/TWI controller"
514 # This is used for the pmic on H3
515 default y if SY8106A_POWER
518 Set this to y to enable the I2C controller which is part of the PRCM.
523 bool "Enable I2C/TWI controller 4"
527 See I2C0_ENABLE help text.
531 bool "Enable support for gpio-s on axp PMICs"
534 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
537 bool "Enable graphical uboot console on HDMI, LCD or VGA"
538 depends on !MACH_SUN8I_A83T
539 depends on !MACH_SUNXI_H3_H5
540 depends on !MACH_SUN8I_R40
541 depends on !MACH_SUN9I
542 depends on !MACH_SUN50I
545 Say Y here to add support for using a cfb console on the HDMI, LCD
546 or VGA output found on most sunxi devices. See doc/README.video for
547 info on how to select the video output and mode.
550 bool "HDMI output support"
551 depends on VIDEO && !MACH_SUN8I
554 Say Y here to add support for outputting video over HDMI.
557 bool "VGA output support"
558 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
561 Say Y here to add support for outputting video over VGA.
563 config VIDEO_VGA_VIA_LCD
564 bool "VGA via LCD controller support"
565 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
568 Say Y here to add support for external DACs connected to the parallel
569 LCD interface driving a VGA connector, such as found on the
572 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
573 bool "Force sync active high for VGA via LCD controller support"
574 depends on VIDEO_VGA_VIA_LCD
577 Say Y here if you've a board which uses opendrain drivers for the vga
578 hsync and vsync signals. Opendrain drivers cannot generate steep enough
579 positive edges for a stable video output, so on boards with opendrain
580 drivers the sync signals must always be active high.
582 config VIDEO_VGA_EXTERNAL_DAC_EN
583 string "LCD panel power enable pin"
584 depends on VIDEO_VGA_VIA_LCD
587 Set the enable pin for the external VGA DAC. This takes a string in the
588 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
590 config VIDEO_COMPOSITE
591 bool "Composite video output support"
592 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
595 Say Y here to add support for outputting composite video.
597 config VIDEO_LCD_MODE
598 string "LCD panel timing details"
602 LCD panel timing details string, leave empty if there is no LCD panel.
603 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
604 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
605 Also see: http://linux-sunxi.org/LCD
607 config VIDEO_LCD_DCLK_PHASE
608 int "LCD panel display clock phase"
612 Select LCD panel display clock phase shift, range 0-3.
614 config VIDEO_LCD_POWER
615 string "LCD panel power enable pin"
619 Set the power enable pin for the LCD panel. This takes a string in the
620 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
622 config VIDEO_LCD_RESET
623 string "LCD panel reset pin"
627 Set the reset pin for the LCD panel. This takes a string in the format
628 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
630 config VIDEO_LCD_BL_EN
631 string "LCD panel backlight enable pin"
635 Set the backlight enable pin for the LCD panel. This takes a string in the
636 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
639 config VIDEO_LCD_BL_PWM
640 string "LCD panel backlight pwm pin"
644 Set the backlight pwm pin for the LCD panel. This takes a string in the
645 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
647 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
648 bool "LCD panel backlight pwm is inverted"
652 Set this if the backlight pwm output is active low.
654 config VIDEO_LCD_PANEL_I2C
655 bool "LCD panel needs to be configured via i2c"
660 Say y here if the LCD panel needs to be configured via i2c. This
661 will add a bitbang i2c controller using gpios to talk to the LCD.
663 config VIDEO_LCD_PANEL_I2C_SDA
664 string "LCD panel i2c interface SDA pin"
665 depends on VIDEO_LCD_PANEL_I2C
668 Set the SDA pin for the LCD i2c interface. This takes a string in the
669 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
671 config VIDEO_LCD_PANEL_I2C_SCL
672 string "LCD panel i2c interface SCL pin"
673 depends on VIDEO_LCD_PANEL_I2C
676 Set the SCL pin for the LCD i2c interface. This takes a string in the
677 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
680 # Note only one of these may be selected at a time! But hidden choices are
681 # not supported by Kconfig
682 config VIDEO_LCD_IF_PARALLEL
685 config VIDEO_LCD_IF_LVDS
690 prompt "LCD panel support"
693 Select which type of LCD panel to support.
695 config VIDEO_LCD_PANEL_PARALLEL
696 bool "Generic parallel interface LCD panel"
697 select VIDEO_LCD_IF_PARALLEL
699 config VIDEO_LCD_PANEL_LVDS
700 bool "Generic lvds interface LCD panel"
701 select VIDEO_LCD_IF_LVDS
703 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
704 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
705 select VIDEO_LCD_SSD2828
706 select VIDEO_LCD_IF_PARALLEL
708 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
710 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
711 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
712 select VIDEO_LCD_ANX9804
713 select VIDEO_LCD_IF_PARALLEL
714 select VIDEO_LCD_PANEL_I2C
716 Select this for eDP LCD panels with 4 lanes running at 1.62G,
717 connected via an ANX9804 bridge chip.
719 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
720 bool "Hitachi tx18d42vm LCD panel"
721 select VIDEO_LCD_HITACHI_TX18D42VM
722 select VIDEO_LCD_IF_LVDS
724 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
726 config VIDEO_LCD_TL059WV5C0
727 bool "tl059wv5c0 LCD panel"
728 select VIDEO_LCD_PANEL_I2C
729 select VIDEO_LCD_IF_PARALLEL
731 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
732 Aigo M60/M608/M606 tablets.
737 string "SATA power pin"
740 Set the pins used to power the SATA. This takes a string in the
741 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
745 int "GMAC Transmit Clock Delay Chain"
748 Set the GMAC Transmit Clock Delay Chain value.
750 config SPL_STACK_R_ADDR
751 default 0x4fe00000 if MACH_SUN4I
752 default 0x4fe00000 if MACH_SUN5I
753 default 0x4fe00000 if MACH_SUN6I
754 default 0x4fe00000 if MACH_SUN7I
755 default 0x4fe00000 if MACH_SUN8I
756 default 0x2fe00000 if MACH_SUN9I
757 default 0x4fe00000 if MACH_SUN50I