4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
61 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
76 bool "sun5i (Allwinner A13)"
78 select ARM_CORTEX_CPU_IS_UP
79 select SUNXI_GEN_SUN4I
83 bool "sun6i (Allwinner A31)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun7i (Allwinner A20)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN4I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A23
103 bool "sun8i (Allwinner A23)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN6I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A33
113 bool "sun8i (Allwinner A33)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
122 config MACH_SUN8I_A83T
123 bool "sun8i (Allwinner A83T)"
125 select SUNXI_GEN_SUN6I
129 bool "sun8i (Allwinner H3)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select MACH_SUNXI_H3_H5
135 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
138 bool "sun9i (Allwinner A80)"
140 select SUNXI_HIGH_SRAM
141 select SUNXI_GEN_SUN6I
145 bool "sun50i (Allwinner A64)"
147 select SUNXI_GEN_SUN6I
148 select SUNXI_HIGH_SRAM
151 config MACH_SUN50I_H5
152 bool "sun50i (Allwinner H5)"
154 select MACH_SUNXI_H3_H5
155 select SUNXI_HIGH_SRAM
159 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
162 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
164 config RESERVE_ALLWINNER_BOOT0_HEADER
165 bool "reserve space for Allwinner boot0 header"
166 select ENABLE_ARM_SOC_BOOT0_HOOK
168 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
169 filled with magic values post build. The Allwinner provided boot0
170 blob relies on this information to load and execute U-Boot.
171 Only needed on 64-bit Allwinner boards so far when using boot0.
173 config ARM_BOOT_HOOK_RMR
177 select ENABLE_ARM_SOC_BOOT0_HOOK
179 Insert some ARM32 code at the very beginning of the U-Boot binary
180 which uses an RMR register write to bring the core into AArch64 mode.
181 The very first instruction acts as a switch, since it's carefully
182 chosen to be a NOP in one mode and a branch in the other, so the
183 code would only be executed if not already in AArch64.
184 This allows both the SPL and the U-Boot proper to be entered in
185 either mode and switch to AArch64 if needed.
188 int "sunxi dram type"
189 depends on MACH_SUN8I_A83T
192 Set the dram type, 3: DDR3, 7: LPDDR3
195 int "sunxi dram clock speed"
196 default 792 if MACH_SUN9I
197 default 312 if MACH_SUN6I || MACH_SUN8I
198 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
199 default 672 if MACH_SUN50I
201 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
202 must be a multiple of 24. For the sun9i (A80), the tested values
203 (for DDR3-1600) are 312 to 792.
205 if MACH_SUN5I || MACH_SUN7I
207 int "sunxi mbus clock speed"
210 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
215 int "sunxi dram zq value"
216 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
217 default 127 if MACH_SUN7I
218 default 4145117 if MACH_SUN9I
219 default 3881915 if MACH_SUN50I
221 Set the dram zq value.
224 bool "sunxi dram odt enable"
225 default n if !MACH_SUN8I_A23
226 default y if MACH_SUN8I_A23
227 default y if MACH_SUN50I
229 Select this to enable dram odt (on die termination).
231 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
233 int "sunxi dram emr1 value"
234 default 0 if MACH_SUN4I
235 default 4 if MACH_SUN5I || MACH_SUN7I
237 Set the dram controller emr1 value.
240 hex "sunxi dram tpr3 value"
243 Set the dram controller tpr3 parameter. This parameter configures
244 the delay on the command lane and also phase shifts, which are
245 applied for sampling incoming read data. The default value 0
246 means that no phase/delay adjustments are necessary. Properly
247 configuring this parameter increases reliability at high DRAM
250 config DRAM_DQS_GATING_DELAY
251 hex "sunxi dram dqs_gating_delay value"
254 Set the dram controller dqs_gating_delay parmeter. Each byte
255 encodes the DQS gating delay for each byte lane. The delay
256 granularity is 1/4 cycle. For example, the value 0x05060606
257 means that the delay is 5 quarter-cycles for one lane (1.25
258 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
259 The default value 0 means autodetection. The results of hardware
260 autodetection are not very reliable and depend on the chip
261 temperature (sometimes producing different results on cold start
262 and warm reboot). But the accuracy of hardware autodetection
263 is usually good enough, unless running at really high DRAM
264 clocks speeds (up to 600MHz). If unsure, keep as 0.
267 prompt "sunxi dram timings"
268 default DRAM_TIMINGS_VENDOR_MAGIC
270 Select the timings of the DDR3 chips.
272 config DRAM_TIMINGS_VENDOR_MAGIC
273 bool "Magic vendor timings from Android"
275 The same DRAM timings as in the Allwinner boot0 bootloader.
277 config DRAM_TIMINGS_DDR3_1066F_1333H
278 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
280 Use the timings of the standard JEDEC DDR3-1066F speed bin for
281 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
282 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
283 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
284 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
285 that down binning to DDR3-1066F is supported (because DDR3-1066F
286 uses a bit faster timings than DDR3-1333H).
288 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
289 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
291 Use the timings of the slowest possible JEDEC speed bin for the
292 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
293 DDR3-800E, DDR3-1066G or DDR3-1333J.
300 config DRAM_ODT_CORRECTION
301 int "sunxi dram odt correction value"
304 Set the dram odt correction value (range -255 - 255). In allwinner
305 fex files, this option is found in bits 8-15 of the u32 odt_en variable
306 in the [dram] section. When bit 31 of the odt_en variable is set
307 then the correction is negative. Usually the value for this is 0.
311 default 816000000 if MACH_SUN50I
312 default 912000000 if MACH_SUN7I
313 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
315 config SYS_CONFIG_NAME
316 default "sun4i" if MACH_SUN4I
317 default "sun5i" if MACH_SUN5I
318 default "sun6i" if MACH_SUN6I
319 default "sun7i" if MACH_SUN7I
320 default "sun8i" if MACH_SUN8I
321 default "sun9i" if MACH_SUN9I
322 default "sun50i" if MACH_SUN50I
331 bool "UART0 on MicroSD breakout board"
334 Repurpose the SD card slot for getting access to the UART0 serial
335 console. Primarily useful only for low level u-boot debugging on
336 tablets, where normal UART0 is difficult to access and requires
337 device disassembly and/or soldering. As the SD card can't be used
338 at the same time, the system can be only booted in the FEL mode.
339 Only enable this if you really know what you are doing.
341 config OLD_SUNXI_KERNEL_COMPAT
342 bool "Enable workarounds for booting old kernels"
345 Set this to enable various workarounds for old kernels, this results in
346 sub-optimal settings for newer kernels, only enable if needed.
349 string "Card detect pin for mmc0"
350 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
353 Set the card detect pin for mmc0, leave empty to not use cd. This
354 takes a string in the format understood by sunxi_name_to_gpio, e.g.
355 PH1 for pin 1 of port H.
358 string "Card detect pin for mmc1"
361 See MMC0_CD_PIN help text.
364 string "Card detect pin for mmc2"
367 See MMC0_CD_PIN help text.
370 string "Card detect pin for mmc3"
373 See MMC0_CD_PIN help text.
376 string "Pins for mmc1"
379 Set the pins used for mmc1, when applicable. This takes a string in the
380 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
383 string "Pins for mmc2"
386 See MMC1_PINS help text.
389 string "Pins for mmc3"
392 See MMC1_PINS help text.
394 config MMC_SUNXI_SLOT_EXTRA
395 int "mmc extra slot number"
398 sunxi builds always enable mmc0, some boards also have a second sdcard
399 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
402 config INITIAL_USB_SCAN_DELAY
403 int "delay initial usb scan by x ms to allow builtin devices to init"
406 Some boards have on board usb devices which need longer than the
407 USB spec's 1 second to connect from board powerup. Set this config
408 option to a non 0 value to add an extra delay before the first usb
412 string "Vbus enable pin for usb0 (otg)"
415 Set the Vbus enable pin for usb0 (otg). This takes a string in the
416 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
419 string "Vbus detect pin for usb0 (otg)"
422 Set the Vbus detect pin for usb0 (otg). This takes a string in the
423 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
426 string "ID detect pin for usb0 (otg)"
429 Set the ID detect pin for usb0 (otg). This takes a string in the
430 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
433 string "Vbus enable pin for usb1 (ehci0)"
434 default "PH6" if MACH_SUN4I || MACH_SUN7I
435 default "PH27" if MACH_SUN6I
437 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
438 a string in the format understood by sunxi_name_to_gpio, e.g.
439 PH1 for pin 1 of port H.
442 string "Vbus enable pin for usb2 (ehci1)"
443 default "PH3" if MACH_SUN4I || MACH_SUN7I
444 default "PH24" if MACH_SUN6I
446 See USB1_VBUS_PIN help text.
449 string "Vbus enable pin for usb3 (ehci2)"
452 See USB1_VBUS_PIN help text.
455 bool "Enable I2C/TWI controller 0"
456 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
457 default n if MACH_SUN6I || MACH_SUN8I
460 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
461 its clock and setting up the bus. This is especially useful on devices
462 with slaves connected to the bus or with pins exposed through e.g. an
463 expansion port/header.
466 bool "Enable I2C/TWI controller 1"
470 See I2C0_ENABLE help text.
473 bool "Enable I2C/TWI controller 2"
477 See I2C0_ENABLE help text.
479 if MACH_SUN6I || MACH_SUN7I
481 bool "Enable I2C/TWI controller 3"
485 See I2C0_ENABLE help text.
490 bool "Enable the PRCM I2C/TWI controller"
491 # This is used for the pmic on H3
492 default y if SY8106A_POWER
495 Set this to y to enable the I2C controller which is part of the PRCM.
500 bool "Enable I2C/TWI controller 4"
504 See I2C0_ENABLE help text.
508 bool "Enable support for gpio-s on axp PMICs"
511 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
514 bool "Enable graphical uboot console on HDMI, LCD or VGA"
515 depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
518 Say Y here to add support for using a cfb console on the HDMI, LCD
519 or VGA output found on most sunxi devices. See doc/README.video for
520 info on how to select the video output and mode.
523 bool "HDMI output support"
524 depends on VIDEO && !MACH_SUN8I
527 Say Y here to add support for outputting video over HDMI.
530 bool "VGA output support"
531 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
534 Say Y here to add support for outputting video over VGA.
536 config VIDEO_VGA_VIA_LCD
537 bool "VGA via LCD controller support"
538 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
541 Say Y here to add support for external DACs connected to the parallel
542 LCD interface driving a VGA connector, such as found on the
545 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
546 bool "Force sync active high for VGA via LCD controller support"
547 depends on VIDEO_VGA_VIA_LCD
550 Say Y here if you've a board which uses opendrain drivers for the vga
551 hsync and vsync signals. Opendrain drivers cannot generate steep enough
552 positive edges for a stable video output, so on boards with opendrain
553 drivers the sync signals must always be active high.
555 config VIDEO_VGA_EXTERNAL_DAC_EN
556 string "LCD panel power enable pin"
557 depends on VIDEO_VGA_VIA_LCD
560 Set the enable pin for the external VGA DAC. This takes a string in the
561 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
563 config VIDEO_COMPOSITE
564 bool "Composite video output support"
565 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
568 Say Y here to add support for outputting composite video.
570 config VIDEO_LCD_MODE
571 string "LCD panel timing details"
575 LCD panel timing details string, leave empty if there is no LCD panel.
576 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
577 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
578 Also see: http://linux-sunxi.org/LCD
580 config VIDEO_LCD_DCLK_PHASE
581 int "LCD panel display clock phase"
585 Select LCD panel display clock phase shift, range 0-3.
587 config VIDEO_LCD_POWER
588 string "LCD panel power enable pin"
592 Set the power enable pin for the LCD panel. This takes a string in the
593 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
595 config VIDEO_LCD_RESET
596 string "LCD panel reset pin"
600 Set the reset pin for the LCD panel. This takes a string in the format
601 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
603 config VIDEO_LCD_BL_EN
604 string "LCD panel backlight enable pin"
608 Set the backlight enable pin for the LCD panel. This takes a string in the
609 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
612 config VIDEO_LCD_BL_PWM
613 string "LCD panel backlight pwm pin"
617 Set the backlight pwm pin for the LCD panel. This takes a string in the
618 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
620 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
621 bool "LCD panel backlight pwm is inverted"
625 Set this if the backlight pwm output is active low.
627 config VIDEO_LCD_PANEL_I2C
628 bool "LCD panel needs to be configured via i2c"
633 Say y here if the LCD panel needs to be configured via i2c. This
634 will add a bitbang i2c controller using gpios to talk to the LCD.
636 config VIDEO_LCD_PANEL_I2C_SDA
637 string "LCD panel i2c interface SDA pin"
638 depends on VIDEO_LCD_PANEL_I2C
641 Set the SDA pin for the LCD i2c interface. This takes a string in the
642 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
644 config VIDEO_LCD_PANEL_I2C_SCL
645 string "LCD panel i2c interface SCL pin"
646 depends on VIDEO_LCD_PANEL_I2C
649 Set the SCL pin for the LCD i2c interface. This takes a string in the
650 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
653 # Note only one of these may be selected at a time! But hidden choices are
654 # not supported by Kconfig
655 config VIDEO_LCD_IF_PARALLEL
658 config VIDEO_LCD_IF_LVDS
663 prompt "LCD panel support"
666 Select which type of LCD panel to support.
668 config VIDEO_LCD_PANEL_PARALLEL
669 bool "Generic parallel interface LCD panel"
670 select VIDEO_LCD_IF_PARALLEL
672 config VIDEO_LCD_PANEL_LVDS
673 bool "Generic lvds interface LCD panel"
674 select VIDEO_LCD_IF_LVDS
676 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
677 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
678 select VIDEO_LCD_SSD2828
679 select VIDEO_LCD_IF_PARALLEL
681 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
683 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
684 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
685 select VIDEO_LCD_ANX9804
686 select VIDEO_LCD_IF_PARALLEL
687 select VIDEO_LCD_PANEL_I2C
689 Select this for eDP LCD panels with 4 lanes running at 1.62G,
690 connected via an ANX9804 bridge chip.
692 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
693 bool "Hitachi tx18d42vm LCD panel"
694 select VIDEO_LCD_HITACHI_TX18D42VM
695 select VIDEO_LCD_IF_LVDS
697 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
699 config VIDEO_LCD_TL059WV5C0
700 bool "tl059wv5c0 LCD panel"
701 select VIDEO_LCD_PANEL_I2C
702 select VIDEO_LCD_IF_PARALLEL
704 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
705 Aigo M60/M608/M606 tablets.
711 int "GMAC Transmit Clock Delay Chain"
714 Set the GMAC Transmit Clock Delay Chain value.
716 config SPL_STACK_R_ADDR
717 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
718 default 0x2fe00000 if MACH_SUN9I