2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
15 #ifdef CONFIG_AXP209_POWER
18 #include <asm/arch/clock.h>
19 #include <asm/arch/dram.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 /* add board specific code here */
30 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
32 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
33 debug("id_pfr1: 0x%08x\n", id_pfr1);
34 /* Generic Timer Extension available? */
35 if ((id_pfr1 >> 16) & 0xf) {
36 debug("Setting CNTFRQ\n");
37 /* CNTFRQ == 24 MHz */
38 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
46 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
51 #ifdef CONFIG_GENERIC_MMC
52 static void mmc_pinmux_setup(int sdc)
58 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
59 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
60 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
61 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
62 sunxi_gpio_set_drv(pin, 2);
67 /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
68 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
69 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
70 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
71 sunxi_gpio_set_drv(pin, 2);
76 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
77 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
78 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
79 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
80 sunxi_gpio_set_drv(pin, 2);
85 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
86 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
87 sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
88 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
89 sunxi_gpio_set_drv(pin, 2);
94 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
99 int board_mmc_init(bd_t *bis)
101 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
102 sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
103 #if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
104 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
105 sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
112 void i2c_init_board(void)
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
115 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
116 clock_twi_onoff(0, 1);
119 #ifdef CONFIG_SPL_BUILD
120 void sunxi_board_init(void)
122 int power_failed = 0;
123 unsigned long ramsize;
125 #ifdef CONFIG_AXP209_POWER
126 power_failed |= axp209_init();
127 power_failed |= axp209_set_dcdc2(1400);
128 power_failed |= axp209_set_dcdc3(1250);
129 power_failed |= axp209_set_ldo2(3000);
130 power_failed |= axp209_set_ldo3(2800);
131 power_failed |= axp209_set_ldo4(2800);
135 ramsize = sunxi_dram_init();
136 printf(" %lu MiB\n", ramsize >> 20);
141 * Only clock up the CPU to full speed if we are reasonably
142 * assured it's being powered with suitable core voltage
145 clock_set_pll1(CONFIG_CLK_FULL_SPEED);
147 printf("Failed to set core voltage! Can't set CPU frequency\n");