2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
26 #include <asm/armv7.h>
31 #include <environment.h>
37 #include <asm/setup.h>
39 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
40 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
41 int soft_i2c_gpio_sda;
42 int soft_i2c_gpio_scl;
44 static int soft_i2c_board_init(void)
48 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
49 if (soft_i2c_gpio_sda < 0) {
50 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
52 return soft_i2c_gpio_sda;
54 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
56 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
57 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
61 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
62 if (soft_i2c_gpio_scl < 0) {
63 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
65 return soft_i2c_gpio_scl;
67 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
69 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
70 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
77 static int soft_i2c_board_init(void) { return 0; }
80 DECLARE_GLOBAL_DATA_PTR;
82 void i2c_init_board(void)
84 #ifdef CONFIG_I2C0_ENABLE
85 #if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN5I) || \
87 defined(CONFIG_MACH_SUN7I) || \
88 defined(CONFIG_MACH_SUN8I_R40)
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
91 clock_twi_onoff(0, 1);
92 #elif defined(CONFIG_MACH_SUN6I)
93 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
95 clock_twi_onoff(0, 1);
96 #elif defined(CONFIG_MACH_SUN8I)
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
99 clock_twi_onoff(0, 1);
103 #ifdef CONFIG_I2C1_ENABLE
104 #if defined(CONFIG_MACH_SUN4I) || \
105 defined(CONFIG_MACH_SUN7I) || \
106 defined(CONFIG_MACH_SUN8I_R40)
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
109 clock_twi_onoff(1, 1);
110 #elif defined(CONFIG_MACH_SUN5I)
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
113 clock_twi_onoff(1, 1);
114 #elif defined(CONFIG_MACH_SUN6I)
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
117 clock_twi_onoff(1, 1);
118 #elif defined(CONFIG_MACH_SUN8I)
119 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
121 clock_twi_onoff(1, 1);
125 #ifdef CONFIG_I2C2_ENABLE
126 #if defined(CONFIG_MACH_SUN4I) || \
127 defined(CONFIG_MACH_SUN7I) || \
128 defined(CONFIG_MACH_SUN8I_R40)
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
131 clock_twi_onoff(2, 1);
132 #elif defined(CONFIG_MACH_SUN5I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
135 clock_twi_onoff(2, 1);
136 #elif defined(CONFIG_MACH_SUN6I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
139 clock_twi_onoff(2, 1);
140 #elif defined(CONFIG_MACH_SUN8I)
141 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
143 clock_twi_onoff(2, 1);
147 #ifdef CONFIG_I2C3_ENABLE
148 #if defined(CONFIG_MACH_SUN6I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
151 clock_twi_onoff(3, 1);
152 #elif defined(CONFIG_MACH_SUN7I) || \
153 defined(CONFIG_MACH_SUN8I_R40)
154 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
156 clock_twi_onoff(3, 1);
160 #ifdef CONFIG_I2C4_ENABLE
161 #if defined(CONFIG_MACH_SUN7I) || \
162 defined(CONFIG_MACH_SUN8I_R40)
163 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
165 clock_twi_onoff(4, 1);
169 #ifdef CONFIG_R_I2C_ENABLE
170 clock_twi_onoff(5, 1);
171 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
172 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
176 /* add board specific code here */
179 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
181 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
184 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
185 debug("id_pfr1: 0x%08x\n", id_pfr1);
186 /* Generic Timer Extension available? */
187 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
190 debug("Setting CNTFRQ\n");
193 * CNTFRQ is a secure register, so we will crash if we try to
194 * write this from the non-secure world (read is OK, though).
195 * In case some bootcode has already set the correct value,
196 * we avoid the risk of writing to it.
198 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
199 if (freq != COUNTER_FREQUENCY) {
200 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
201 freq, COUNTER_FREQUENCY);
202 #ifdef CONFIG_NON_SECURE
203 printf("arch timer frequency is wrong, but cannot adjust it\n");
205 asm volatile("mcr p15, 0, %0, c14, c0, 0"
206 : : "r"(COUNTER_FREQUENCY));
210 #endif /* !CONFIG_ARM64 */
212 ret = axp_gpio_init();
216 #ifdef CONFIG_SATAPWR
217 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
218 gpio_request(satapwr_pin, "satapwr");
219 gpio_direction_output(satapwr_pin, 1);
220 /* Give attached sata device time to power-up to avoid link timeouts */
224 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
225 gpio_request(macpwr_pin, "macpwr");
226 gpio_direction_output(macpwr_pin, 1);
231 * Temporary workaround for enabling I2C clocks until proper sunxi DM
232 * clk, reset and pinctrl drivers land.
237 /* Uses dm gpio code so do this here and not in i2c_init_board() */
238 return soft_i2c_board_init();
243 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
248 #if defined(CONFIG_NAND_SUNXI)
249 static void nand_pinmux_setup(void)
253 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
254 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
256 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
257 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
258 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
260 /* sun4i / sun7i do have a PC23, but it is not used for nand,
261 * only sun7i has a PC24 */
262 #ifdef CONFIG_MACH_SUN7I
263 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
267 static void nand_clock_setup(void)
269 struct sunxi_ccm_reg *const ccm =
270 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
272 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
273 #ifdef CONFIG_MACH_SUN9I
274 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
276 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
278 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
281 void board_nand_init(void)
285 #ifndef CONFIG_SPL_BUILD
292 static void mmc_pinmux_setup(int sdc)
295 __maybe_unused int pins;
300 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
301 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
302 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
303 sunxi_gpio_set_drv(pin, 2);
308 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
310 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
311 defined(CONFIG_MACH_SUN8I_R40)
312 if (pins == SUNXI_GPIO_H) {
313 /* SDC1: PH22-PH-27 */
314 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
315 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
316 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
317 sunxi_gpio_set_drv(pin, 2);
321 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
322 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
323 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
324 sunxi_gpio_set_drv(pin, 2);
327 #elif defined(CONFIG_MACH_SUN5I)
329 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
330 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
331 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
332 sunxi_gpio_set_drv(pin, 2);
334 #elif defined(CONFIG_MACH_SUN6I)
336 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
337 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
338 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
339 sunxi_gpio_set_drv(pin, 2);
341 #elif defined(CONFIG_MACH_SUN8I)
342 if (pins == SUNXI_GPIO_D) {
344 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
345 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
346 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
347 sunxi_gpio_set_drv(pin, 2);
351 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
352 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
353 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
354 sunxi_gpio_set_drv(pin, 2);
361 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
363 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
365 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
366 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
367 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
368 sunxi_gpio_set_drv(pin, 2);
370 #elif defined(CONFIG_MACH_SUN5I)
371 if (pins == SUNXI_GPIO_E) {
373 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
374 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
375 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
376 sunxi_gpio_set_drv(pin, 2);
380 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
381 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
382 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
383 sunxi_gpio_set_drv(pin, 2);
386 #elif defined(CONFIG_MACH_SUN6I)
387 if (pins == SUNXI_GPIO_A) {
389 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
390 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
391 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
392 sunxi_gpio_set_drv(pin, 2);
395 /* SDC2: PC6-PC15, PC24 */
396 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
397 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
399 sunxi_gpio_set_drv(pin, 2);
402 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
403 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
404 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
406 #elif defined(CONFIG_MACH_SUN8I_R40)
407 /* SDC2: PC6-PC15, PC24 */
408 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
409 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
410 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
411 sunxi_gpio_set_drv(pin, 2);
414 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
415 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
417 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
418 /* SDC2: PC5-PC6, PC8-PC16 */
419 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
420 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
421 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
422 sunxi_gpio_set_drv(pin, 2);
425 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
426 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
427 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
428 sunxi_gpio_set_drv(pin, 2);
430 #elif defined(CONFIG_MACH_SUN9I)
432 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
433 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
434 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
435 sunxi_gpio_set_drv(pin, 2);
441 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
443 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
444 defined(CONFIG_MACH_SUN8I_R40)
446 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
447 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
448 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
449 sunxi_gpio_set_drv(pin, 2);
451 #elif defined(CONFIG_MACH_SUN6I)
452 if (pins == SUNXI_GPIO_A) {
454 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
455 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
456 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
457 sunxi_gpio_set_drv(pin, 2);
460 /* SDC3: PC6-PC15, PC24 */
461 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
462 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
463 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
464 sunxi_gpio_set_drv(pin, 2);
467 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
468 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
469 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
475 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
480 int board_mmc_init(bd_t *bis)
482 __maybe_unused struct mmc *mmc0, *mmc1;
483 __maybe_unused char buf[512];
485 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
486 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
490 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
491 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
492 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
501 #ifdef CONFIG_SPL_BUILD
502 void sunxi_board_init(void)
504 int power_failed = 0;
506 #ifdef CONFIG_SY8106A_POWER
507 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
510 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
511 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
512 defined CONFIG_AXP818_POWER
513 power_failed = axp_init();
515 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
516 defined CONFIG_AXP818_POWER
517 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
519 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
520 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
521 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
522 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
524 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
525 defined CONFIG_AXP818_POWER
526 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
529 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
530 defined CONFIG_AXP818_POWER
531 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
533 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
534 #if !defined(CONFIG_AXP152_POWER)
535 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
537 #ifdef CONFIG_AXP209_POWER
538 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
541 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
542 defined(CONFIG_AXP818_POWER)
543 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
544 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
545 #if !defined CONFIG_AXP809_POWER
546 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
547 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
549 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
550 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
551 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
554 #ifdef CONFIG_AXP818_POWER
555 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
556 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
557 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
560 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
561 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
565 gd->ram_size = sunxi_dram_init();
566 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
571 * Only clock up the CPU to full speed if we are reasonably
572 * assured it's being powered with suitable core voltage
575 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
577 printf("Failed to set core voltage! Can't set CPU frequency\n");
581 #ifdef CONFIG_USB_GADGET
582 int g_dnl_board_usb_cable_connected(void)
584 return sunxi_usb_phy_vbus_detect(0);
588 #ifdef CONFIG_SERIAL_TAG
589 void get_board_serial(struct tag_serialnr *serialnr)
592 unsigned long long serial;
594 serial_string = env_get("serial#");
597 serial = simple_strtoull(serial_string, NULL, 16);
599 serialnr->high = (unsigned int) (serial >> 32);
600 serialnr->low = (unsigned int) (serial & 0xffffffff);
609 * Check the SPL header for the "sunxi" variant. If found: parse values
610 * that might have been passed by the loader ("fel" utility), and update
611 * the environment accordingly.
613 static void parse_spl_header(const uint32_t spl_addr)
615 struct boot_file_head *spl = (void *)(ulong)spl_addr;
616 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
617 return; /* signature mismatch, no usable header */
619 uint8_t spl_header_version = spl->spl_signature[3];
620 if (spl_header_version != SPL_HEADER_VERSION) {
621 printf("sunxi SPL version mismatch: expected %u, got %u\n",
622 SPL_HEADER_VERSION, spl_header_version);
625 if (!spl->fel_script_address)
628 if (spl->fel_uEnv_length != 0) {
630 * data is expected in uEnv.txt compatible format, so "env
631 * import -t" the string(s) at fel_script_address right away.
633 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
634 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
637 /* otherwise assume .scr format (mkimage-type script) */
638 env_set_hex("fel_scriptaddr", spl->fel_script_address);
642 * Note this function gets called multiple times.
643 * It must not make any changes to env variables which already exist.
645 static void setup_environment(const void *fdt)
647 char serial_string[17] = { 0 };
653 ret = sunxi_get_sid(sid);
654 if (ret == 0 && sid[0] != 0) {
656 * The single words 1 - 3 of the SID have quite a few bits
657 * which are the same on many models, so we take a crc32
658 * of all 3 words, to get a more unique value.
660 * Note we only do this on newer SoCs as we cannot change
661 * the algorithm on older SoCs since those have been using
662 * fixed mac-addresses based on only using word 3 for a
663 * long time and changing a fixed mac-address with an
664 * u-boot update is not good.
666 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
667 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
668 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
669 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
672 /* Ensure the NIC specific bytes of the mac are not all 0 */
673 if ((sid[3] & 0xffffff) == 0)
676 for (i = 0; i < 4; i++) {
677 sprintf(ethaddr, "ethernet%d", i);
678 if (!fdt_get_alias(fdt, ethaddr))
682 strcpy(ethaddr, "ethaddr");
684 sprintf(ethaddr, "eth%daddr", i);
686 if (env_get(ethaddr))
689 /* Non OUI / registered MAC address */
690 mac_addr[0] = (i << 4) | 0x02;
691 mac_addr[1] = (sid[0] >> 0) & 0xff;
692 mac_addr[2] = (sid[3] >> 24) & 0xff;
693 mac_addr[3] = (sid[3] >> 16) & 0xff;
694 mac_addr[4] = (sid[3] >> 8) & 0xff;
695 mac_addr[5] = (sid[3] >> 0) & 0xff;
697 eth_env_set_enetaddr(ethaddr, mac_addr);
700 if (!env_get("serial#")) {
701 snprintf(serial_string, sizeof(serial_string),
702 "%08x%08x", sid[0], sid[3]);
704 env_set("serial#", serial_string);
709 int misc_init_r(void)
711 __maybe_unused int ret;
714 env_set("fel_booted", NULL);
715 env_set("fel_scriptaddr", NULL);
716 env_set("mmc_bootdev", NULL);
718 boot = sunxi_get_boot_device();
719 /* determine if we are running in FEL mode */
720 if (boot == BOOT_DEVICE_BOARD) {
721 env_set("fel_booted", "1");
722 parse_spl_header(SPL_ADDR);
723 /* or if we booted from MMC, and which one */
724 } else if (boot == BOOT_DEVICE_MMC1) {
725 env_set("mmc_bootdev", "0");
726 } else if (boot == BOOT_DEVICE_MMC2) {
727 env_set("mmc_bootdev", "1");
730 setup_environment(gd->fdt_blob);
732 #ifndef CONFIG_MACH_SUN9I
733 ret = sunxi_usb_phy_probe();
738 #ifdef CONFIG_USB_ETHER
745 int ft_board_setup(void *blob, bd_t *bd)
747 int __maybe_unused r;
750 * Call setup_environment again in case the boot fdt has
751 * ethernet aliases the u-boot copy does not have.
753 setup_environment(blob);
755 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
756 r = sunxi_simplefb_setup(blob);
763 #ifdef CONFIG_SPL_LOAD_FIT
764 int board_fit_config_name_match(const char *name)
766 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
767 const char *cmp_str = (void *)(ulong)SPL_ADDR;
769 /* Check if there is a DT name stored in the SPL header and use that. */
770 if (spl->dt_name_offset) {
771 cmp_str += spl->dt_name_offset;
773 #ifdef CONFIG_DEFAULT_DEVICE_TREE
774 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
780 /* Differentiate the two Pine64 board DTs by their DRAM size. */
781 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
782 if ((gd->ram_size > 512 * 1024 * 1024))
783 return !strstr(name, "plus");
785 return !!strstr(name, "plus");
787 return strcmp(name, cmp_str);