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1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <spl.h>
15 #include <serial.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/clk_synthesizer.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/io.h>
27 #include <asm/emif.h>
28 #include <asm/gpio.h>
29 #include <asm/omap_common.h>
30 #include <asm/omap_sec_common.h>
31 #include <asm/omap_mmc.h>
32 #include <i2c.h>
33 #include <miiphy.h>
34 #include <cpsw.h>
35 #include <power/tps65217.h>
36 #include <power/tps65910.h>
37 #include <environment.h>
38 #include <watchdog.h>
39 #include <environment.h>
40 #include "../common/board_detect.h"
41 #include "board.h"
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 /* GPIO that controls power to DDR on EVM-SK */
46 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
47 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
48 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
49 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
50 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
51 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
52 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
53 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
54 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
55
56 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
57
58 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
59 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
60
61 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
62 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
63
64 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
65 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
66
67 /*
68  * Read header information from EEPROM into global structure.
69  */
70 #ifdef CONFIG_TI_I2C_BOARD_DETECT
71 void do_board_detect(void)
72 {
73         enable_i2c0_pin_mux();
74         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
75
76         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
77                                  CONFIG_EEPROM_CHIP_ADDRESS))
78                 printf("ti_i2c_eeprom_init failed\n");
79 }
80 #endif
81
82 #ifndef CONFIG_DM_SERIAL
83 struct serial_device *default_serial_console(void)
84 {
85         if (board_is_icev2())
86                 return &eserial4_device;
87         else
88                 return &eserial1_device;
89 }
90 #endif
91
92 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
93 static const struct ddr_data ddr2_data = {
94         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
95         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
96         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
97 };
98
99 static const struct cmd_control ddr2_cmd_ctrl_data = {
100         .cmd0csratio = MT47H128M16RT25E_RATIO,
101
102         .cmd1csratio = MT47H128M16RT25E_RATIO,
103
104         .cmd2csratio = MT47H128M16RT25E_RATIO,
105 };
106
107 static const struct emif_regs ddr2_emif_reg_data = {
108         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
109         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
110         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
111         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
112         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
113         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
114 };
115
116 static const struct emif_regs ddr2_evm_emif_reg_data = {
117         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
118         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
119         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
120         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
121         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
122         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
123         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
124 };
125
126 static const struct ddr_data ddr3_data = {
127         .datardsratio0 = MT41J128MJT125_RD_DQS,
128         .datawdsratio0 = MT41J128MJT125_WR_DQS,
129         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
130         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
131 };
132
133 static const struct ddr_data ddr3_beagleblack_data = {
134         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
135         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
136         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
137         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
138 };
139
140 static const struct ddr_data ddr3_evm_data = {
141         .datardsratio0 = MT41J512M8RH125_RD_DQS,
142         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
143         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
144         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
145 };
146
147 static const struct ddr_data ddr3_icev2_data = {
148         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
149         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
150         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
151         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
152 };
153
154 static const struct cmd_control ddr3_cmd_ctrl_data = {
155         .cmd0csratio = MT41J128MJT125_RATIO,
156         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
157
158         .cmd1csratio = MT41J128MJT125_RATIO,
159         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
160
161         .cmd2csratio = MT41J128MJT125_RATIO,
162         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
163 };
164
165 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
166         .cmd0csratio = MT41K256M16HA125E_RATIO,
167         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
168
169         .cmd1csratio = MT41K256M16HA125E_RATIO,
170         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
171
172         .cmd2csratio = MT41K256M16HA125E_RATIO,
173         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
174 };
175
176 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
177         .cmd0csratio = MT41J512M8RH125_RATIO,
178         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
179
180         .cmd1csratio = MT41J512M8RH125_RATIO,
181         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
182
183         .cmd2csratio = MT41J512M8RH125_RATIO,
184         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
185 };
186
187 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
188         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
189         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
190
191         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
192         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
193
194         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
195         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
196 };
197
198 static struct emif_regs ddr3_emif_reg_data = {
199         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
200         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
201         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
202         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
203         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
204         .zq_config = MT41J128MJT125_ZQ_CFG,
205         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
206                                 PHY_EN_DYN_PWRDN,
207 };
208
209 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
210         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
211         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
212         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
213         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
214         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
215         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
216         .zq_config = MT41K256M16HA125E_ZQ_CFG,
217         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
218 };
219
220 static struct emif_regs ddr3_evm_emif_reg_data = {
221         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
222         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
223         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
224         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
225         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
226         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
227         .zq_config = MT41J512M8RH125_ZQ_CFG,
228         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
229                                 PHY_EN_DYN_PWRDN,
230 };
231
232 static struct emif_regs ddr3_icev2_emif_reg_data = {
233         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
234         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
235         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
236         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
237         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
238         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
239         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
240                                 PHY_EN_DYN_PWRDN,
241 };
242
243 #ifdef CONFIG_SPL_OS_BOOT
244 int spl_start_uboot(void)
245 {
246         /* break into full u-boot on 'c' */
247         if (serial_tstc() && serial_getc() == 'c')
248                 return 1;
249
250 #ifdef CONFIG_SPL_ENV_SUPPORT
251         env_init();
252         env_relocate_spec();
253         if (getenv_yesno("boot_os") != 1)
254                 return 1;
255 #endif
256
257         return 0;
258 }
259 #endif
260
261 const struct dpll_params *get_dpll_ddr_params(void)
262 {
263         int ind = get_sys_clk_index();
264
265         if (board_is_evm_sk())
266                 return &dpll_ddr3_303MHz[ind];
267         else if (board_is_bone_lt() || board_is_icev2())
268                 return &dpll_ddr3_400MHz[ind];
269         else if (board_is_evm_15_or_later())
270                 return &dpll_ddr3_303MHz[ind];
271         else
272                 return &dpll_ddr2_266MHz[ind];
273 }
274
275 static u8 bone_not_connected_to_ac_power(void)
276 {
277         if (board_is_bone()) {
278                 uchar pmic_status_reg;
279                 if (tps65217_reg_read(TPS65217_STATUS,
280                                       &pmic_status_reg))
281                         return 1;
282                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
283                         puts("No AC power, switching to default OPP\n");
284                         return 1;
285                 }
286         }
287         return 0;
288 }
289
290 const struct dpll_params *get_dpll_mpu_params(void)
291 {
292         int ind = get_sys_clk_index();
293         int freq = am335x_get_efuse_mpu_max_freq(cdev);
294
295         if (bone_not_connected_to_ac_power())
296                 freq = MPUPLL_M_600;
297
298         if (board_is_bone_lt())
299                 freq = MPUPLL_M_1000;
300
301         switch (freq) {
302         case MPUPLL_M_1000:
303                 return &dpll_mpu_opp[ind][5];
304         case MPUPLL_M_800:
305                 return &dpll_mpu_opp[ind][4];
306         case MPUPLL_M_720:
307                 return &dpll_mpu_opp[ind][3];
308         case MPUPLL_M_600:
309                 return &dpll_mpu_opp[ind][2];
310         case MPUPLL_M_500:
311                 return &dpll_mpu_opp100;
312         case MPUPLL_M_300:
313                 return &dpll_mpu_opp[ind][0];
314         }
315
316         return &dpll_mpu_opp[ind][0];
317 }
318
319 static void scale_vcores_bone(int freq)
320 {
321         int usb_cur_lim, mpu_vdd;
322
323         /*
324          * Only perform PMIC configurations if board rev > A1
325          * on Beaglebone White
326          */
327         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
328                 return;
329
330         if (i2c_probe(TPS65217_CHIP_PM))
331                 return;
332
333         /*
334          * On Beaglebone White we need to ensure we have AC power
335          * before increasing the frequency.
336          */
337         if (bone_not_connected_to_ac_power())
338                 freq = MPUPLL_M_600;
339
340         /*
341          * Override what we have detected since we know if we have
342          * a Beaglebone Black it supports 1GHz.
343          */
344         if (board_is_bone_lt())
345                 freq = MPUPLL_M_1000;
346
347         switch (freq) {
348         case MPUPLL_M_1000:
349                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
350                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
351                 break;
352         case MPUPLL_M_800:
353                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
354                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
355                 break;
356         case MPUPLL_M_720:
357                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
358                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
359                 break;
360         case MPUPLL_M_600:
361         case MPUPLL_M_500:
362         case MPUPLL_M_300:
363         default:
364                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
365                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
366                 break;
367         }
368
369         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
370                                TPS65217_POWER_PATH,
371                                usb_cur_lim,
372                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
373                 puts("tps65217_reg_write failure\n");
374
375         /* Set DCDC3 (CORE) voltage to 1.10V */
376         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
377                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
378                 puts("tps65217_voltage_update failure\n");
379                 return;
380         }
381
382         /* Set DCDC2 (MPU) voltage */
383         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
384                 puts("tps65217_voltage_update failure\n");
385                 return;
386         }
387
388         /*
389          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
390          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
391          */
392         if (board_is_bone()) {
393                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
394                                        TPS65217_DEFLS1,
395                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
396                                        TPS65217_LDO_MASK))
397                         puts("tps65217_reg_write failure\n");
398         } else {
399                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
400                                        TPS65217_DEFLS1,
401                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
402                                        TPS65217_LDO_MASK))
403                         puts("tps65217_reg_write failure\n");
404         }
405
406         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
407                                TPS65217_DEFLS2,
408                                TPS65217_LDO_VOLTAGE_OUT_3_3,
409                                TPS65217_LDO_MASK))
410                 puts("tps65217_reg_write failure\n");
411 }
412
413 void scale_vcores_generic(int freq)
414 {
415         int sil_rev, mpu_vdd;
416
417         /*
418          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
419          * MPU frequencies we support we use a CORE voltage of
420          * 1.10V.  For MPU voltage we need to switch based on
421          * the frequency we are running at.
422          */
423         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
424                 return;
425
426         /*
427          * Depending on MPU clock and PG we will need a different
428          * VDD to drive at that speed.
429          */
430         sil_rev = readl(&cdev->deviceid) >> 28;
431         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
432
433         /* Tell the TPS65910 to use i2c */
434         tps65910_set_i2c_control();
435
436         /* First update MPU voltage. */
437         if (tps65910_voltage_update(MPU, mpu_vdd))
438                 return;
439
440         /* Second, update the CORE voltage. */
441         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
442                 return;
443
444 }
445
446 void gpi2c_init(void)
447 {
448         /* When needed to be invoked prior to BSS initialization */
449         static bool first_time = true;
450
451         if (first_time) {
452                 enable_i2c0_pin_mux();
453                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
454                          CONFIG_SYS_OMAP24_I2C_SLAVE);
455                 first_time = false;
456         }
457 }
458
459 void scale_vcores(void)
460 {
461         int freq;
462
463         gpi2c_init();
464         freq = am335x_get_efuse_mpu_max_freq(cdev);
465
466         if (board_is_beaglebonex())
467                 scale_vcores_bone(freq);
468         else
469                 scale_vcores_generic(freq);
470 }
471
472 void set_uart_mux_conf(void)
473 {
474 #if CONFIG_CONS_INDEX == 1
475         enable_uart0_pin_mux();
476 #elif CONFIG_CONS_INDEX == 2
477         enable_uart1_pin_mux();
478 #elif CONFIG_CONS_INDEX == 3
479         enable_uart2_pin_mux();
480 #elif CONFIG_CONS_INDEX == 4
481         enable_uart3_pin_mux();
482 #elif CONFIG_CONS_INDEX == 5
483         enable_uart4_pin_mux();
484 #elif CONFIG_CONS_INDEX == 6
485         enable_uart5_pin_mux();
486 #endif
487 }
488
489 void set_mux_conf_regs(void)
490 {
491         enable_board_pin_mux();
492 }
493
494 const struct ctrl_ioregs ioregs_evmsk = {
495         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
496         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
497         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
498         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
499         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
500 };
501
502 const struct ctrl_ioregs ioregs_bonelt = {
503         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
504         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
505         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
506         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
507         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
508 };
509
510 const struct ctrl_ioregs ioregs_evm15 = {
511         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
512         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
513         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
514         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
515         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
516 };
517
518 const struct ctrl_ioregs ioregs = {
519         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
520         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
521         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
522         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
523         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
524 };
525
526 void sdram_init(void)
527 {
528         if (board_is_evm_sk()) {
529                 /*
530                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
531                  * This is safe enough to do on older revs.
532                  */
533                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
534                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
535         }
536
537         if (board_is_icev2()) {
538                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
539                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
540         }
541
542         if (board_is_evm_sk())
543                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
544                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
545         else if (board_is_bone_lt())
546                 config_ddr(400, &ioregs_bonelt,
547                            &ddr3_beagleblack_data,
548                            &ddr3_beagleblack_cmd_ctrl_data,
549                            &ddr3_beagleblack_emif_reg_data, 0);
550         else if (board_is_evm_15_or_later())
551                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
552                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
553         else if (board_is_icev2())
554                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
555                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
556                            0);
557         else if (board_is_gp_evm())
558                 config_ddr(266, &ioregs, &ddr2_data,
559                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
560         else
561                 config_ddr(266, &ioregs, &ddr2_data,
562                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
563 }
564 #endif
565
566 #if !defined(CONFIG_SPL_BUILD) || \
567         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
568 static void request_and_set_gpio(int gpio, char *name, int val)
569 {
570         int ret;
571
572         ret = gpio_request(gpio, name);
573         if (ret < 0) {
574                 printf("%s: Unable to request %s\n", __func__, name);
575                 return;
576         }
577
578         ret = gpio_direction_output(gpio, 0);
579         if (ret < 0) {
580                 printf("%s: Unable to set %s  as output\n", __func__, name);
581                 goto err_free_gpio;
582         }
583
584         gpio_set_value(gpio, val);
585
586         return;
587
588 err_free_gpio:
589         gpio_free(gpio);
590 }
591
592 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
593 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
594
595 /**
596  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
597  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
598  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
599  * give 50MHz output for Eth0 and 1.
600  */
601 static struct clk_synth cdce913_data = {
602         .id = 0x81,
603         .capacitor = 0x90,
604         .mux = 0x6d,
605         .pdiv2 = 0x2,
606         .pdiv3 = 0x2,
607 };
608 #endif
609
610 /*
611  * Basic board specific setup.  Pinmux has been handled already.
612  */
613 int board_init(void)
614 {
615 #if defined(CONFIG_HW_WATCHDOG)
616         hw_watchdog_init();
617 #endif
618
619         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
620 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
621         gpmc_init();
622 #endif
623
624 #if !defined(CONFIG_SPL_BUILD) || \
625         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
626         if (board_is_icev2()) {
627                 int rv;
628                 u32 reg;
629
630                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
631                 /* Make J19 status available on GPIO1_26 */
632                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
633
634                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
635                 /*
636                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
637                  * jumpers near the port. Read the jumper value and set
638                  * the pinmux, external mux and PHY clock accordingly.
639                  * As jumper line is overridden by PHY RX_DV pin immediately
640                  * after bootstrap (power-up/reset), we need to sample
641                  * it during PHY reset using GPIO rising edge detection.
642                  */
643                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
644                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
645                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
646                 writel(reg, GPIO0_RISINGDETECT);
647                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
648                 writel(reg, GPIO1_RISINGDETECT);
649                 /* Reset PHYs to capture the Jumper setting */
650                 gpio_set_value(GPIO_PHY_RESET, 0);
651                 udelay(2);      /* PHY datasheet states 1uS min. */
652                 gpio_set_value(GPIO_PHY_RESET, 1);
653
654                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
655                 if (reg) {
656                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
657                         /* RMII mode */
658                         printf("ETH0, CPSW\n");
659                 } else {
660                         /* MII mode */
661                         printf("ETH0, PRU\n");
662                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
663                 }
664
665                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
666                 if (reg) {
667                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
668                         /* RMII mode */
669                         printf("ETH1, CPSW\n");
670                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
671                 } else {
672                         /* MII mode */
673                         printf("ETH1, PRU\n");
674                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
675                 }
676
677                 /* disable rising edge IRQs */
678                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
679                 writel(reg, GPIO0_RISINGDETECT);
680                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
681                 writel(reg, GPIO1_RISINGDETECT);
682
683                 rv = setup_clock_synthesizer(&cdce913_data);
684                 if (rv) {
685                         printf("Clock synthesizer setup failed %d\n", rv);
686                         return rv;
687                 }
688
689                 /* reset PHYs */
690                 gpio_set_value(GPIO_PHY_RESET, 0);
691                 udelay(2);      /* PHY datasheet states 1uS min. */
692                 gpio_set_value(GPIO_PHY_RESET, 1);
693         }
694 #endif
695
696         return 0;
697 }
698
699 #ifdef CONFIG_BOARD_LATE_INIT
700 int board_late_init(void)
701 {
702 #if !defined(CONFIG_SPL_BUILD)
703         uint8_t mac_addr[6];
704         uint32_t mac_hi, mac_lo;
705 #endif
706
707 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
708         char *name = NULL;
709
710         if (board_is_bone_lt()) {
711                 /* BeagleBoard.org BeagleBone Black Wireless: */
712                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
713                         name = "BBBW";
714                 }
715                 /* SeeedStudio BeagleBone Green Wireless */
716                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
717                         name = "BBGW";
718                 }
719                 /* BeagleBoard.org BeagleBone Blue */
720                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
721                         name = "BBBL";
722                 }
723         }
724
725         if (board_is_bbg1())
726                 name = "BBG1";
727         set_board_info_env(name);
728
729         /*
730          * Default FIT boot on HS devices. Non FIT images are not allowed
731          * on HS devices.
732          */
733         if (get_device_type() == HS_DEVICE)
734                 setenv("boot_fit", "1");
735 #endif
736
737 #if !defined(CONFIG_SPL_BUILD)
738         /* try reading mac address from efuse */
739         mac_lo = readl(&cdev->macid0l);
740         mac_hi = readl(&cdev->macid0h);
741         mac_addr[0] = mac_hi & 0xFF;
742         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
743         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
744         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
745         mac_addr[4] = mac_lo & 0xFF;
746         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
747
748         if (!getenv("ethaddr")) {
749                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
750
751                 if (is_valid_ethaddr(mac_addr))
752                         eth_setenv_enetaddr("ethaddr", mac_addr);
753         }
754
755         mac_lo = readl(&cdev->macid1l);
756         mac_hi = readl(&cdev->macid1h);
757         mac_addr[0] = mac_hi & 0xFF;
758         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
759         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
760         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
761         mac_addr[4] = mac_lo & 0xFF;
762         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
763
764         if (!getenv("eth1addr")) {
765                 if (is_valid_ethaddr(mac_addr))
766                         eth_setenv_enetaddr("eth1addr", mac_addr);
767         }
768 #endif
769
770         return 0;
771 }
772 #endif
773
774 #ifndef CONFIG_DM_ETH
775
776 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
777         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
778 static void cpsw_control(int enabled)
779 {
780         /* VTP can be added here */
781
782         return;
783 }
784
785 static struct cpsw_slave_data cpsw_slaves[] = {
786         {
787                 .slave_reg_ofs  = 0x208,
788                 .sliver_reg_ofs = 0xd80,
789                 .phy_addr       = 0,
790         },
791         {
792                 .slave_reg_ofs  = 0x308,
793                 .sliver_reg_ofs = 0xdc0,
794                 .phy_addr       = 1,
795         },
796 };
797
798 static struct cpsw_platform_data cpsw_data = {
799         .mdio_base              = CPSW_MDIO_BASE,
800         .cpsw_base              = CPSW_BASE,
801         .mdio_div               = 0xff,
802         .channels               = 8,
803         .cpdma_reg_ofs          = 0x800,
804         .slaves                 = 1,
805         .slave_data             = cpsw_slaves,
806         .ale_reg_ofs            = 0xd00,
807         .ale_entries            = 1024,
808         .host_port_reg_ofs      = 0x108,
809         .hw_stats_reg_ofs       = 0x900,
810         .bd_ram_ofs             = 0x2000,
811         .mac_control            = (1 << 5),
812         .control                = cpsw_control,
813         .host_port_num          = 0,
814         .version                = CPSW_CTRL_VERSION_2,
815 };
816 #endif
817
818 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
819         defined(CONFIG_SPL_BUILD)) || \
820         ((defined(CONFIG_DRIVER_TI_CPSW) || \
821           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
822          !defined(CONFIG_SPL_BUILD))
823
824 /*
825  * This function will:
826  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
827  * in the environment
828  * Perform fixups to the PHY present on certain boards.  We only need this
829  * function in:
830  * - SPL with either CPSW or USB ethernet support
831  * - Full U-Boot, with either CPSW or USB ethernet
832  * Build in only these cases to avoid warnings about unused variables
833  * when we build an SPL that has neither option but full U-Boot will.
834  */
835 int board_eth_init(bd_t *bis)
836 {
837         int rv, n = 0;
838 #if defined(CONFIG_USB_ETHER) && \
839         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
840         uint8_t mac_addr[6];
841         uint32_t mac_hi, mac_lo;
842
843         /*
844          * use efuse mac address for USB ethernet as we know that
845          * both CPSW and USB ethernet will never be active at the same time
846          */
847         mac_lo = readl(&cdev->macid0l);
848         mac_hi = readl(&cdev->macid0h);
849         mac_addr[0] = mac_hi & 0xFF;
850         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
851         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
852         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
853         mac_addr[4] = mac_lo & 0xFF;
854         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
855 #endif
856
857
858 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
859         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
860
861 #ifdef CONFIG_DRIVER_TI_CPSW
862         if (board_is_bone() || board_is_bone_lt() ||
863             board_is_idk()) {
864                 writel(MII_MODE_ENABLE, &cdev->miisel);
865                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
866                                 PHY_INTERFACE_MODE_MII;
867         } else if (board_is_icev2()) {
868                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
869                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
870                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
871                 cpsw_slaves[0].phy_addr = 1;
872                 cpsw_slaves[1].phy_addr = 3;
873         } else {
874                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
875                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
876                                 PHY_INTERFACE_MODE_RGMII;
877         }
878
879         rv = cpsw_register(&cpsw_data);
880         if (rv < 0)
881                 printf("Error %d registering CPSW switch\n", rv);
882         else
883                 n += rv;
884 #endif
885
886         /*
887          *
888          * CPSW RGMII Internal Delay Mode is not supported in all PVT
889          * operating points.  So we must set the TX clock delay feature
890          * in the AR8051 PHY.  Since we only support a single ethernet
891          * device in U-Boot, we only do this for the first instance.
892          */
893 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
894 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
895 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
896 #define AR8051_RGMII_TX_CLK_DLY         0x100
897
898         if (board_is_evm_sk() || board_is_gp_evm()) {
899                 const char *devname;
900                 devname = miiphy_get_current_dev();
901
902                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
903                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
904                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
905                                 AR8051_RGMII_TX_CLK_DLY);
906         }
907 #endif
908 #if defined(CONFIG_USB_ETHER) && \
909         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
910         if (is_valid_ethaddr(mac_addr))
911                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
912
913         rv = usb_eth_initialize(bis);
914         if (rv < 0)
915                 printf("Error %d registering USB_ETHER\n", rv);
916         else
917                 n += rv;
918 #endif
919         return n;
920 }
921 #endif
922
923 #endif /* CONFIG_DM_ETH */
924
925 #ifdef CONFIG_SPL_LOAD_FIT
926 int board_fit_config_name_match(const char *name)
927 {
928         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
929                 return 0;
930         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
931                 return 0;
932         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
933                 return 0;
934         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
935                 return 0;
936         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
937                 return 0;
938         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
939                 return 0;
940         else
941                 return -1;
942 }
943 #endif
944
945 #ifdef CONFIG_TI_SECURE_DEVICE
946 void board_fit_image_post_process(void **p_image, size_t *p_size)
947 {
948         secure_boot_verify_image(p_image, p_size);
949 }
950 #endif
951
952 #if !CONFIG_IS_ENABLED(OF_CONTROL)
953 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
954         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
955         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
956         .cfg.f_min = 400000,
957         .cfg.f_max = 52000000,
958         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
959         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
960 };
961
962 U_BOOT_DEVICE(am335x_mmc0) = {
963         .name = "omap_hsmmc",
964         .platdata = &am335x_mmc0_platdata,
965 };
966
967 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
968         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
969         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
970         .cfg.f_min = 400000,
971         .cfg.f_max = 52000000,
972         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
973         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
974 };
975
976 U_BOOT_DEVICE(am335x_mmc1) = {
977         .name = "omap_hsmmc",
978         .platdata = &am335x_mmc1_platdata,
979 };
980 #endif