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[u-boot] / board / ti / am335x / board.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board.c
4  *
5  * Board functions for TI AM335X based boards
6  *
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8  */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <spl.h>
14 #include <serial.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/clk_synthesizer.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <asm/omap_common.h>
29 #include <asm/omap_sec_common.h>
30 #include <asm/omap_mmc.h>
31 #include <i2c.h>
32 #include <miiphy.h>
33 #include <cpsw.h>
34 #include <power/tps65217.h>
35 #include <power/tps65910.h>
36 #include <environment.h>
37 #include <watchdog.h>
38 #include <environment.h>
39 #include "../common/board_detect.h"
40 #include "board.h"
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 /* GPIO that controls power to DDR on EVM-SK */
45 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
46 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
47 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
48 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
49 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
50 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
51 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
52 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
53 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
54
55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
56
57 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
58 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
59
60 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
61 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
62
63 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
64 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
65
66 /*
67  * Read header information from EEPROM into global structure.
68  */
69 #ifdef CONFIG_TI_I2C_BOARD_DETECT
70 void do_board_detect(void)
71 {
72         enable_i2c0_pin_mux();
73         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
74
75         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
76                                  CONFIG_EEPROM_CHIP_ADDRESS))
77                 printf("ti_i2c_eeprom_init failed\n");
78 }
79 #endif
80
81 #ifndef CONFIG_DM_SERIAL
82 struct serial_device *default_serial_console(void)
83 {
84         if (board_is_icev2())
85                 return &eserial4_device;
86         else
87                 return &eserial1_device;
88 }
89 #endif
90
91 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
92 static const struct ddr_data ddr2_data = {
93         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
94         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
95         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
96 };
97
98 static const struct cmd_control ddr2_cmd_ctrl_data = {
99         .cmd0csratio = MT47H128M16RT25E_RATIO,
100
101         .cmd1csratio = MT47H128M16RT25E_RATIO,
102
103         .cmd2csratio = MT47H128M16RT25E_RATIO,
104 };
105
106 static const struct emif_regs ddr2_emif_reg_data = {
107         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
108         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
109         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
110         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
111         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
112         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
113 };
114
115 static const struct emif_regs ddr2_evm_emif_reg_data = {
116         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
117         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
118         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
119         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
120         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
121         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
122         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
123 };
124
125 static const struct ddr_data ddr3_data = {
126         .datardsratio0 = MT41J128MJT125_RD_DQS,
127         .datawdsratio0 = MT41J128MJT125_WR_DQS,
128         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
129         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
130 };
131
132 static const struct ddr_data ddr3_beagleblack_data = {
133         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
134         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
135         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
136         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
137 };
138
139 static const struct ddr_data ddr3_evm_data = {
140         .datardsratio0 = MT41J512M8RH125_RD_DQS,
141         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
142         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
143         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
144 };
145
146 static const struct ddr_data ddr3_icev2_data = {
147         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
148         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
149         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
150         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
151 };
152
153 static const struct cmd_control ddr3_cmd_ctrl_data = {
154         .cmd0csratio = MT41J128MJT125_RATIO,
155         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
156
157         .cmd1csratio = MT41J128MJT125_RATIO,
158         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
159
160         .cmd2csratio = MT41J128MJT125_RATIO,
161         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
162 };
163
164 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
165         .cmd0csratio = MT41K256M16HA125E_RATIO,
166         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
167
168         .cmd1csratio = MT41K256M16HA125E_RATIO,
169         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
170
171         .cmd2csratio = MT41K256M16HA125E_RATIO,
172         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
173 };
174
175 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
176         .cmd0csratio = MT41J512M8RH125_RATIO,
177         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
178
179         .cmd1csratio = MT41J512M8RH125_RATIO,
180         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
181
182         .cmd2csratio = MT41J512M8RH125_RATIO,
183         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
184 };
185
186 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
187         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
188         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
189
190         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
191         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
192
193         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
194         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
195 };
196
197 static struct emif_regs ddr3_emif_reg_data = {
198         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
199         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
200         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
201         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
202         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
203         .zq_config = MT41J128MJT125_ZQ_CFG,
204         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
205                                 PHY_EN_DYN_PWRDN,
206 };
207
208 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
209         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
210         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
211         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
212         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
213         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
214         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
215         .zq_config = MT41K256M16HA125E_ZQ_CFG,
216         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
217 };
218
219 static struct emif_regs ddr3_evm_emif_reg_data = {
220         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
221         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
222         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
223         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
224         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
225         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
226         .zq_config = MT41J512M8RH125_ZQ_CFG,
227         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
228                                 PHY_EN_DYN_PWRDN,
229 };
230
231 static struct emif_regs ddr3_icev2_emif_reg_data = {
232         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
233         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
234         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
235         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
236         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
237         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
238         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
239                                 PHY_EN_DYN_PWRDN,
240 };
241
242 #ifdef CONFIG_SPL_OS_BOOT
243 int spl_start_uboot(void)
244 {
245 #ifdef CONFIG_SPL_SERIAL_SUPPORT
246         /* break into full u-boot on 'c' */
247         if (serial_tstc() && serial_getc() == 'c')
248                 return 1;
249 #endif
250
251 #ifdef CONFIG_SPL_ENV_SUPPORT
252         env_init();
253         env_load();
254         if (env_get_yesno("boot_os") != 1)
255                 return 1;
256 #endif
257
258         return 0;
259 }
260 #endif
261
262 const struct dpll_params *get_dpll_ddr_params(void)
263 {
264         int ind = get_sys_clk_index();
265
266         if (board_is_evm_sk())
267                 return &dpll_ddr3_303MHz[ind];
268         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
269                 return &dpll_ddr3_400MHz[ind];
270         else if (board_is_evm_15_or_later())
271                 return &dpll_ddr3_303MHz[ind];
272         else
273                 return &dpll_ddr2_266MHz[ind];
274 }
275
276 static u8 bone_not_connected_to_ac_power(void)
277 {
278         if (board_is_bone()) {
279                 uchar pmic_status_reg;
280                 if (tps65217_reg_read(TPS65217_STATUS,
281                                       &pmic_status_reg))
282                         return 1;
283                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
284                         puts("No AC power, switching to default OPP\n");
285                         return 1;
286                 }
287         }
288         return 0;
289 }
290
291 const struct dpll_params *get_dpll_mpu_params(void)
292 {
293         int ind = get_sys_clk_index();
294         int freq = am335x_get_efuse_mpu_max_freq(cdev);
295
296         if (bone_not_connected_to_ac_power())
297                 freq = MPUPLL_M_600;
298
299         if (board_is_pb() || board_is_bone_lt())
300                 freq = MPUPLL_M_1000;
301
302         switch (freq) {
303         case MPUPLL_M_1000:
304                 return &dpll_mpu_opp[ind][5];
305         case MPUPLL_M_800:
306                 return &dpll_mpu_opp[ind][4];
307         case MPUPLL_M_720:
308                 return &dpll_mpu_opp[ind][3];
309         case MPUPLL_M_600:
310                 return &dpll_mpu_opp[ind][2];
311         case MPUPLL_M_500:
312                 return &dpll_mpu_opp100;
313         case MPUPLL_M_300:
314                 return &dpll_mpu_opp[ind][0];
315         }
316
317         return &dpll_mpu_opp[ind][0];
318 }
319
320 static void scale_vcores_bone(int freq)
321 {
322         int usb_cur_lim, mpu_vdd;
323
324         /*
325          * Only perform PMIC configurations if board rev > A1
326          * on Beaglebone White
327          */
328         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
329                 return;
330
331         if (i2c_probe(TPS65217_CHIP_PM))
332                 return;
333
334         /*
335          * On Beaglebone White we need to ensure we have AC power
336          * before increasing the frequency.
337          */
338         if (bone_not_connected_to_ac_power())
339                 freq = MPUPLL_M_600;
340
341         /*
342          * Override what we have detected since we know if we have
343          * a Beaglebone Black it supports 1GHz.
344          */
345         if (board_is_pb() || board_is_bone_lt())
346                 freq = MPUPLL_M_1000;
347
348         switch (freq) {
349         case MPUPLL_M_1000:
350                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
351                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
352                 break;
353         case MPUPLL_M_800:
354                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
355                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
356                 break;
357         case MPUPLL_M_720:
358                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
359                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
360                 break;
361         case MPUPLL_M_600:
362         case MPUPLL_M_500:
363         case MPUPLL_M_300:
364         default:
365                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
366                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
367                 break;
368         }
369
370         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
371                                TPS65217_POWER_PATH,
372                                usb_cur_lim,
373                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
374                 puts("tps65217_reg_write failure\n");
375
376         /* Set DCDC3 (CORE) voltage to 1.10V */
377         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
378                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
379                 puts("tps65217_voltage_update failure\n");
380                 return;
381         }
382
383         /* Set DCDC2 (MPU) voltage */
384         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
385                 puts("tps65217_voltage_update failure\n");
386                 return;
387         }
388
389         /*
390          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
391          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
392          */
393         if (board_is_bone()) {
394                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
395                                        TPS65217_DEFLS1,
396                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
397                                        TPS65217_LDO_MASK))
398                         puts("tps65217_reg_write failure\n");
399         } else {
400                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
401                                        TPS65217_DEFLS1,
402                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
403                                        TPS65217_LDO_MASK))
404                         puts("tps65217_reg_write failure\n");
405         }
406
407         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
408                                TPS65217_DEFLS2,
409                                TPS65217_LDO_VOLTAGE_OUT_3_3,
410                                TPS65217_LDO_MASK))
411                 puts("tps65217_reg_write failure\n");
412 }
413
414 void scale_vcores_generic(int freq)
415 {
416         int sil_rev, mpu_vdd;
417
418         /*
419          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
420          * MPU frequencies we support we use a CORE voltage of
421          * 1.10V.  For MPU voltage we need to switch based on
422          * the frequency we are running at.
423          */
424         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
425                 return;
426
427         /*
428          * Depending on MPU clock and PG we will need a different
429          * VDD to drive at that speed.
430          */
431         sil_rev = readl(&cdev->deviceid) >> 28;
432         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
433
434         /* Tell the TPS65910 to use i2c */
435         tps65910_set_i2c_control();
436
437         /* First update MPU voltage. */
438         if (tps65910_voltage_update(MPU, mpu_vdd))
439                 return;
440
441         /* Second, update the CORE voltage. */
442         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
443                 return;
444
445 }
446
447 void gpi2c_init(void)
448 {
449         /* When needed to be invoked prior to BSS initialization */
450         static bool first_time = true;
451
452         if (first_time) {
453                 enable_i2c0_pin_mux();
454                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
455                          CONFIG_SYS_OMAP24_I2C_SLAVE);
456                 first_time = false;
457         }
458 }
459
460 void scale_vcores(void)
461 {
462         int freq;
463
464         gpi2c_init();
465         freq = am335x_get_efuse_mpu_max_freq(cdev);
466
467         if (board_is_beaglebonex())
468                 scale_vcores_bone(freq);
469         else
470                 scale_vcores_generic(freq);
471 }
472
473 void set_uart_mux_conf(void)
474 {
475 #if CONFIG_CONS_INDEX == 1
476         enable_uart0_pin_mux();
477 #elif CONFIG_CONS_INDEX == 2
478         enable_uart1_pin_mux();
479 #elif CONFIG_CONS_INDEX == 3
480         enable_uart2_pin_mux();
481 #elif CONFIG_CONS_INDEX == 4
482         enable_uart3_pin_mux();
483 #elif CONFIG_CONS_INDEX == 5
484         enable_uart4_pin_mux();
485 #elif CONFIG_CONS_INDEX == 6
486         enable_uart5_pin_mux();
487 #endif
488 }
489
490 void set_mux_conf_regs(void)
491 {
492         enable_board_pin_mux();
493 }
494
495 const struct ctrl_ioregs ioregs_evmsk = {
496         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
497         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
498         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
499         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
500         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
501 };
502
503 const struct ctrl_ioregs ioregs_bonelt = {
504         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
505         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
506         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
507         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
508         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
509 };
510
511 const struct ctrl_ioregs ioregs_evm15 = {
512         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
513         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
514         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
515         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
516         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
517 };
518
519 const struct ctrl_ioregs ioregs = {
520         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
521         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
522         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
523         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
524         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
525 };
526
527 void sdram_init(void)
528 {
529         if (board_is_evm_sk()) {
530                 /*
531                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
532                  * This is safe enough to do on older revs.
533                  */
534                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
535                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
536         }
537
538         if (board_is_icev2()) {
539                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
540                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
541         }
542
543         if (board_is_evm_sk())
544                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
545                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
546         else if (board_is_pb() || board_is_bone_lt())
547                 config_ddr(400, &ioregs_bonelt,
548                            &ddr3_beagleblack_data,
549                            &ddr3_beagleblack_cmd_ctrl_data,
550                            &ddr3_beagleblack_emif_reg_data, 0);
551         else if (board_is_evm_15_or_later())
552                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
553                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
554         else if (board_is_icev2())
555                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
556                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
557                            0);
558         else if (board_is_gp_evm())
559                 config_ddr(266, &ioregs, &ddr2_data,
560                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
561         else
562                 config_ddr(266, &ioregs, &ddr2_data,
563                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
564 }
565 #endif
566
567 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
568         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
569 static void request_and_set_gpio(int gpio, char *name, int val)
570 {
571         int ret;
572
573         ret = gpio_request(gpio, name);
574         if (ret < 0) {
575                 printf("%s: Unable to request %s\n", __func__, name);
576                 return;
577         }
578
579         ret = gpio_direction_output(gpio, 0);
580         if (ret < 0) {
581                 printf("%s: Unable to set %s  as output\n", __func__, name);
582                 goto err_free_gpio;
583         }
584
585         gpio_set_value(gpio, val);
586
587         return;
588
589 err_free_gpio:
590         gpio_free(gpio);
591 }
592
593 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
594 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
595
596 /**
597  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
598  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
599  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
600  * give 50MHz output for Eth0 and 1.
601  */
602 static struct clk_synth cdce913_data = {
603         .id = 0x81,
604         .capacitor = 0x90,
605         .mux = 0x6d,
606         .pdiv2 = 0x2,
607         .pdiv3 = 0x2,
608 };
609 #endif
610
611 /*
612  * Basic board specific setup.  Pinmux has been handled already.
613  */
614 int board_init(void)
615 {
616 #if defined(CONFIG_HW_WATCHDOG)
617         hw_watchdog_init();
618 #endif
619
620         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
621 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
622         gpmc_init();
623 #endif
624
625 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
626         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
627         if (board_is_icev2()) {
628                 int rv;
629                 u32 reg;
630
631                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
632                 /* Make J19 status available on GPIO1_26 */
633                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
634
635                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
636                 /*
637                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
638                  * jumpers near the port. Read the jumper value and set
639                  * the pinmux, external mux and PHY clock accordingly.
640                  * As jumper line is overridden by PHY RX_DV pin immediately
641                  * after bootstrap (power-up/reset), we need to sample
642                  * it during PHY reset using GPIO rising edge detection.
643                  */
644                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
645                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
646                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
647                 writel(reg, GPIO0_RISINGDETECT);
648                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
649                 writel(reg, GPIO1_RISINGDETECT);
650                 /* Reset PHYs to capture the Jumper setting */
651                 gpio_set_value(GPIO_PHY_RESET, 0);
652                 udelay(2);      /* PHY datasheet states 1uS min. */
653                 gpio_set_value(GPIO_PHY_RESET, 1);
654
655                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
656                 if (reg) {
657                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
658                         /* RMII mode */
659                         printf("ETH0, CPSW\n");
660                 } else {
661                         /* MII mode */
662                         printf("ETH0, PRU\n");
663                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
664                 }
665
666                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
667                 if (reg) {
668                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
669                         /* RMII mode */
670                         printf("ETH1, CPSW\n");
671                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
672                 } else {
673                         /* MII mode */
674                         printf("ETH1, PRU\n");
675                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
676                 }
677
678                 /* disable rising edge IRQs */
679                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
680                 writel(reg, GPIO0_RISINGDETECT);
681                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
682                 writel(reg, GPIO1_RISINGDETECT);
683
684                 rv = setup_clock_synthesizer(&cdce913_data);
685                 if (rv) {
686                         printf("Clock synthesizer setup failed %d\n", rv);
687                         return rv;
688                 }
689
690                 /* reset PHYs */
691                 gpio_set_value(GPIO_PHY_RESET, 0);
692                 udelay(2);      /* PHY datasheet states 1uS min. */
693                 gpio_set_value(GPIO_PHY_RESET, 1);
694         }
695 #endif
696
697         return 0;
698 }
699
700 #ifdef CONFIG_BOARD_LATE_INIT
701 int board_late_init(void)
702 {
703 #if !defined(CONFIG_SPL_BUILD)
704         uint8_t mac_addr[6];
705         uint32_t mac_hi, mac_lo;
706 #endif
707
708 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
709         char *name = NULL;
710
711         if (board_is_bone_lt()) {
712                 /* BeagleBoard.org BeagleBone Black Wireless: */
713                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
714                         name = "BBBW";
715                 }
716                 /* SeeedStudio BeagleBone Green Wireless */
717                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
718                         name = "BBGW";
719                 }
720                 /* BeagleBoard.org BeagleBone Blue */
721                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
722                         name = "BBBL";
723                 }
724         }
725
726         if (board_is_bbg1())
727                 name = "BBG1";
728         set_board_info_env(name);
729
730         /*
731          * Default FIT boot on HS devices. Non FIT images are not allowed
732          * on HS devices.
733          */
734         if (get_device_type() == HS_DEVICE)
735                 env_set("boot_fit", "1");
736 #endif
737
738 #if !defined(CONFIG_SPL_BUILD)
739         /* try reading mac address from efuse */
740         mac_lo = readl(&cdev->macid0l);
741         mac_hi = readl(&cdev->macid0h);
742         mac_addr[0] = mac_hi & 0xFF;
743         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
744         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
745         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
746         mac_addr[4] = mac_lo & 0xFF;
747         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
748
749         if (!env_get("ethaddr")) {
750                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
751
752                 if (is_valid_ethaddr(mac_addr))
753                         eth_env_set_enetaddr("ethaddr", mac_addr);
754         }
755
756         mac_lo = readl(&cdev->macid1l);
757         mac_hi = readl(&cdev->macid1h);
758         mac_addr[0] = mac_hi & 0xFF;
759         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
760         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
761         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
762         mac_addr[4] = mac_lo & 0xFF;
763         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
764
765         if (!env_get("eth1addr")) {
766                 if (is_valid_ethaddr(mac_addr))
767                         eth_env_set_enetaddr("eth1addr", mac_addr);
768         }
769 #endif
770
771         if (!env_get("serial#")) {
772                 char *board_serial = env_get("board_serial");
773                 char *ethaddr = env_get("ethaddr");
774
775                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
776                         env_set("serial#", ethaddr);
777                 else
778                         env_set("serial#", board_serial);
779         }
780
781         return 0;
782 }
783 #endif
784
785 #ifndef CONFIG_DM_ETH
786
787 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
788         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
789 static void cpsw_control(int enabled)
790 {
791         /* VTP can be added here */
792
793         return;
794 }
795
796 static struct cpsw_slave_data cpsw_slaves[] = {
797         {
798                 .slave_reg_ofs  = 0x208,
799                 .sliver_reg_ofs = 0xd80,
800                 .phy_addr       = 0,
801         },
802         {
803                 .slave_reg_ofs  = 0x308,
804                 .sliver_reg_ofs = 0xdc0,
805                 .phy_addr       = 1,
806         },
807 };
808
809 static struct cpsw_platform_data cpsw_data = {
810         .mdio_base              = CPSW_MDIO_BASE,
811         .cpsw_base              = CPSW_BASE,
812         .mdio_div               = 0xff,
813         .channels               = 8,
814         .cpdma_reg_ofs          = 0x800,
815         .slaves                 = 1,
816         .slave_data             = cpsw_slaves,
817         .ale_reg_ofs            = 0xd00,
818         .ale_entries            = 1024,
819         .host_port_reg_ofs      = 0x108,
820         .hw_stats_reg_ofs       = 0x900,
821         .bd_ram_ofs             = 0x2000,
822         .mac_control            = (1 << 5),
823         .control                = cpsw_control,
824         .host_port_num          = 0,
825         .version                = CPSW_CTRL_VERSION_2,
826 };
827 #endif
828
829 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
830         defined(CONFIG_SPL_BUILD)) || \
831         ((defined(CONFIG_DRIVER_TI_CPSW) || \
832           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
833          !defined(CONFIG_SPL_BUILD))
834
835 /*
836  * This function will:
837  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
838  * in the environment
839  * Perform fixups to the PHY present on certain boards.  We only need this
840  * function in:
841  * - SPL with either CPSW or USB ethernet support
842  * - Full U-Boot, with either CPSW or USB ethernet
843  * Build in only these cases to avoid warnings about unused variables
844  * when we build an SPL that has neither option but full U-Boot will.
845  */
846 int board_eth_init(bd_t *bis)
847 {
848         int rv, n = 0;
849 #if defined(CONFIG_USB_ETHER) && \
850         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
851         uint8_t mac_addr[6];
852         uint32_t mac_hi, mac_lo;
853
854         /*
855          * use efuse mac address for USB ethernet as we know that
856          * both CPSW and USB ethernet will never be active at the same time
857          */
858         mac_lo = readl(&cdev->macid0l);
859         mac_hi = readl(&cdev->macid0h);
860         mac_addr[0] = mac_hi & 0xFF;
861         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
862         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
863         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
864         mac_addr[4] = mac_lo & 0xFF;
865         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
866 #endif
867
868
869 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
870         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
871
872 #ifdef CONFIG_DRIVER_TI_CPSW
873         if (board_is_bone() || board_is_bone_lt() ||
874             board_is_idk()) {
875                 writel(MII_MODE_ENABLE, &cdev->miisel);
876                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
877                                 PHY_INTERFACE_MODE_MII;
878         } else if (board_is_icev2()) {
879                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
880                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
881                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
882                 cpsw_slaves[0].phy_addr = 1;
883                 cpsw_slaves[1].phy_addr = 3;
884         } else {
885                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
886                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
887                                 PHY_INTERFACE_MODE_RGMII;
888         }
889
890         rv = cpsw_register(&cpsw_data);
891         if (rv < 0)
892                 printf("Error %d registering CPSW switch\n", rv);
893         else
894                 n += rv;
895 #endif
896
897         /*
898          *
899          * CPSW RGMII Internal Delay Mode is not supported in all PVT
900          * operating points.  So we must set the TX clock delay feature
901          * in the AR8051 PHY.  Since we only support a single ethernet
902          * device in U-Boot, we only do this for the first instance.
903          */
904 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
905 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
906 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
907 #define AR8051_RGMII_TX_CLK_DLY         0x100
908
909         if (board_is_evm_sk() || board_is_gp_evm()) {
910                 const char *devname;
911                 devname = miiphy_get_current_dev();
912
913                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
914                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
915                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
916                                 AR8051_RGMII_TX_CLK_DLY);
917         }
918 #endif
919 #if defined(CONFIG_USB_ETHER) && \
920         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
921         if (is_valid_ethaddr(mac_addr))
922                 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
923
924         rv = usb_eth_initialize(bis);
925         if (rv < 0)
926                 printf("Error %d registering USB_ETHER\n", rv);
927         else
928                 n += rv;
929 #endif
930         return n;
931 }
932 #endif
933
934 #endif /* CONFIG_DM_ETH */
935
936 #ifdef CONFIG_SPL_LOAD_FIT
937 int board_fit_config_name_match(const char *name)
938 {
939         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
940                 return 0;
941         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
942                 return 0;
943         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
944                 return 0;
945         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
946                 return 0;
947         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
948                 return 0;
949         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
950                 return 0;
951         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
952                 return 0;
953         else
954                 return -1;
955 }
956 #endif
957
958 #ifdef CONFIG_TI_SECURE_DEVICE
959 void board_fit_image_post_process(void **p_image, size_t *p_size)
960 {
961         secure_boot_verify_image(p_image, p_size);
962 }
963 #endif
964
965 #if !CONFIG_IS_ENABLED(OF_CONTROL)
966 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
967         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
968         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
969         .cfg.f_min = 400000,
970         .cfg.f_max = 52000000,
971         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
972         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
973 };
974
975 U_BOOT_DEVICE(am335x_mmc0) = {
976         .name = "omap_hsmmc",
977         .platdata = &am335x_mmc0_platdata,
978 };
979
980 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
981         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
982         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
983         .cfg.f_min = 400000,
984         .cfg.f_max = 52000000,
985         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
986         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
987 };
988
989 U_BOOT_DEVICE(am335x_mmc1) = {
990         .name = "omap_hsmmc",
991         .platdata = &am335x_mmc1_platdata,
992 };
993 #endif