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1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <errno.h>
13 #include <spl.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include <asm/io.h>
24 #include <asm/emif.h>
25 #include <asm/gpio.h>
26 #include <i2c.h>
27 #include <miiphy.h>
28 #include <cpsw.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
31 #include <environment.h>
32 #include <watchdog.h>
33 #include <environment.h>
34 #include "../common/board_detect.h"
35 #include "board.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /* GPIO that controls power to DDR on EVM-SK */
40 #define GPIO_DDR_VTT_EN         7
41
42 #if defined(CONFIG_SPL_BUILD) || \
43         (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
44 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
45 #endif
46
47 /*
48  * Read header information from EEPROM into global structure.
49  */
50 static inline int __maybe_unused read_eeprom(void)
51 {
52         return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
53 }
54
55 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
56 static const struct ddr_data ddr2_data = {
57         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
58         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
59         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
60 };
61
62 static const struct cmd_control ddr2_cmd_ctrl_data = {
63         .cmd0csratio = MT47H128M16RT25E_RATIO,
64
65         .cmd1csratio = MT47H128M16RT25E_RATIO,
66
67         .cmd2csratio = MT47H128M16RT25E_RATIO,
68 };
69
70 static const struct emif_regs ddr2_emif_reg_data = {
71         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
72         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
73         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
74         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
75         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
76         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
77 };
78
79 static const struct ddr_data ddr3_data = {
80         .datardsratio0 = MT41J128MJT125_RD_DQS,
81         .datawdsratio0 = MT41J128MJT125_WR_DQS,
82         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
83         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
84 };
85
86 static const struct ddr_data ddr3_beagleblack_data = {
87         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
88         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
89         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
90         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
91 };
92
93 static const struct ddr_data ddr3_evm_data = {
94         .datardsratio0 = MT41J512M8RH125_RD_DQS,
95         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
96         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
97         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
98 };
99
100 static const struct cmd_control ddr3_cmd_ctrl_data = {
101         .cmd0csratio = MT41J128MJT125_RATIO,
102         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
103
104         .cmd1csratio = MT41J128MJT125_RATIO,
105         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
106
107         .cmd2csratio = MT41J128MJT125_RATIO,
108         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
109 };
110
111 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
112         .cmd0csratio = MT41K256M16HA125E_RATIO,
113         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
114
115         .cmd1csratio = MT41K256M16HA125E_RATIO,
116         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
117
118         .cmd2csratio = MT41K256M16HA125E_RATIO,
119         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
120 };
121
122 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
123         .cmd0csratio = MT41J512M8RH125_RATIO,
124         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
125
126         .cmd1csratio = MT41J512M8RH125_RATIO,
127         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
128
129         .cmd2csratio = MT41J512M8RH125_RATIO,
130         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
131 };
132
133 static struct emif_regs ddr3_emif_reg_data = {
134         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
135         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
136         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
137         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
138         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
139         .zq_config = MT41J128MJT125_ZQ_CFG,
140         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
141                                 PHY_EN_DYN_PWRDN,
142 };
143
144 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
145         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
146         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
147         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
148         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
149         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
150         .zq_config = MT41K256M16HA125E_ZQ_CFG,
151         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
152 };
153
154 static struct emif_regs ddr3_evm_emif_reg_data = {
155         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
156         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
157         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
158         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
159         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
160         .zq_config = MT41J512M8RH125_ZQ_CFG,
161         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
162                                 PHY_EN_DYN_PWRDN,
163 };
164
165 #ifdef CONFIG_SPL_OS_BOOT
166 int spl_start_uboot(void)
167 {
168         /* break into full u-boot on 'c' */
169         if (serial_tstc() && serial_getc() == 'c')
170                 return 1;
171
172 #ifdef CONFIG_SPL_ENV_SUPPORT
173         env_init();
174         env_relocate_spec();
175         if (getenv_yesno("boot_os") != 1)
176                 return 1;
177 #endif
178
179         return 0;
180 }
181 #endif
182
183 #define OSC     (V_OSCK/1000000)
184 const struct dpll_params dpll_ddr = {
185                 266, OSC-1, 1, -1, -1, -1, -1};
186 const struct dpll_params dpll_ddr_evm_sk = {
187                 303, OSC-1, 1, -1, -1, -1, -1};
188 const struct dpll_params dpll_ddr_bone_black = {
189                 400, OSC-1, 1, -1, -1, -1, -1};
190
191 void am33xx_spl_board_init(void)
192 {
193         int mpu_vdd;
194
195         if (read_eeprom() < 0)
196                 puts("Could not get board ID.\n");
197
198         /* Get the frequency */
199         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
200
201         if (board_is_bone() || board_is_bone_lt()) {
202                 /* BeagleBone PMIC Code */
203                 int usb_cur_lim;
204
205                 /*
206                  * Only perform PMIC configurations if board rev > A1
207                  * on Beaglebone White
208                  */
209                 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
210                         return;
211
212                 if (i2c_probe(TPS65217_CHIP_PM))
213                         return;
214
215                 /*
216                  * On Beaglebone White we need to ensure we have AC power
217                  * before increasing the frequency.
218                  */
219                 if (board_is_bone()) {
220                         uchar pmic_status_reg;
221                         if (tps65217_reg_read(TPS65217_STATUS,
222                                               &pmic_status_reg))
223                                 return;
224                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
225                                 puts("No AC power, disabling frequency switch\n");
226                                 return;
227                         }
228                 }
229
230                 /*
231                  * Override what we have detected since we know if we have
232                  * a Beaglebone Black it supports 1GHz.
233                  */
234                 if (board_is_bone_lt())
235                         dpll_mpu_opp100.m = MPUPLL_M_1000;
236
237                 /*
238                  * Increase USB current limit to 1300mA or 1800mA and set
239                  * the MPU voltage controller as needed.
240                  */
241                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
242                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
243                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
244                 } else {
245                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
246                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
247                 }
248
249                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
250                                        TPS65217_POWER_PATH,
251                                        usb_cur_lim,
252                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
253                         puts("tps65217_reg_write failure\n");
254
255                 /* Set DCDC3 (CORE) voltage to 1.125V */
256                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
257                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
258                         puts("tps65217_voltage_update failure\n");
259                         return;
260                 }
261
262                 /* Set CORE Frequencies to OPP100 */
263                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
264
265                 /* Set DCDC2 (MPU) voltage */
266                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
267                         puts("tps65217_voltage_update failure\n");
268                         return;
269                 }
270
271                 /*
272                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
273                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
274                  */
275                 if (board_is_bone()) {
276                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
277                                                TPS65217_DEFLS1,
278                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
279                                                TPS65217_LDO_MASK))
280                                 puts("tps65217_reg_write failure\n");
281                 } else {
282                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
283                                                TPS65217_DEFLS1,
284                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
285                                                TPS65217_LDO_MASK))
286                                 puts("tps65217_reg_write failure\n");
287                 }
288
289                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
290                                        TPS65217_DEFLS2,
291                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
292                                        TPS65217_LDO_MASK))
293                         puts("tps65217_reg_write failure\n");
294         } else {
295                 int sil_rev;
296
297                 /*
298                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
299                  * MPU frequencies we support we use a CORE voltage of
300                  * 1.1375V.  For MPU voltage we need to switch based on
301                  * the frequency we are running at.
302                  */
303                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
304                         return;
305
306                 /*
307                  * Depending on MPU clock and PG we will need a different
308                  * VDD to drive at that speed.
309                  */
310                 sil_rev = readl(&cdev->deviceid) >> 28;
311                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
312                                                       dpll_mpu_opp100.m);
313
314                 /* Tell the TPS65910 to use i2c */
315                 tps65910_set_i2c_control();
316
317                 /* First update MPU voltage. */
318                 if (tps65910_voltage_update(MPU, mpu_vdd))
319                         return;
320
321                 /* Second, update the CORE voltage. */
322                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
323                         return;
324
325                 /* Set CORE Frequencies to OPP100 */
326                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
327         }
328
329         /* Set MPU Frequency to what we detected now that voltages are set */
330         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
331 }
332
333 const struct dpll_params *get_dpll_ddr_params(void)
334 {
335         enable_i2c0_pin_mux();
336         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
337         if (read_eeprom() < 0)
338                 puts("Could not get board ID.\n");
339
340         if (board_is_evm_sk())
341                 return &dpll_ddr_evm_sk;
342         else if (board_is_bone_lt())
343                 return &dpll_ddr_bone_black;
344         else if (board_is_evm_15_or_later())
345                 return &dpll_ddr_evm_sk;
346         else
347                 return &dpll_ddr;
348 }
349
350 void set_uart_mux_conf(void)
351 {
352 #if CONFIG_CONS_INDEX == 1
353         enable_uart0_pin_mux();
354 #elif CONFIG_CONS_INDEX == 2
355         enable_uart1_pin_mux();
356 #elif CONFIG_CONS_INDEX == 3
357         enable_uart2_pin_mux();
358 #elif CONFIG_CONS_INDEX == 4
359         enable_uart3_pin_mux();
360 #elif CONFIG_CONS_INDEX == 5
361         enable_uart4_pin_mux();
362 #elif CONFIG_CONS_INDEX == 6
363         enable_uart5_pin_mux();
364 #endif
365 }
366
367 void set_mux_conf_regs(void)
368 {
369         if (read_eeprom() < 0)
370                 puts("Could not get board ID.\n");
371
372         enable_board_pin_mux();
373 }
374
375 const struct ctrl_ioregs ioregs_evmsk = {
376         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
377         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
378         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
379         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
380         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
381 };
382
383 const struct ctrl_ioregs ioregs_bonelt = {
384         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
385         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
386         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
387         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
388         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
389 };
390
391 const struct ctrl_ioregs ioregs_evm15 = {
392         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
393         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
394         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
395         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
396         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
397 };
398
399 const struct ctrl_ioregs ioregs = {
400         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
401         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
402         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
403         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
404         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
405 };
406
407 void sdram_init(void)
408 {
409         if (read_eeprom() < 0)
410                 puts("Could not get board ID.\n");
411
412         if (board_is_evm_sk()) {
413                 /*
414                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
415                  * This is safe enough to do on older revs.
416                  */
417                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
418                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
419         }
420
421         if (board_is_evm_sk())
422                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
423                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
424         else if (board_is_bone_lt())
425                 config_ddr(400, &ioregs_bonelt,
426                            &ddr3_beagleblack_data,
427                            &ddr3_beagleblack_cmd_ctrl_data,
428                            &ddr3_beagleblack_emif_reg_data, 0);
429         else if (board_is_evm_15_or_later())
430                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
431                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
432         else
433                 config_ddr(266, &ioregs, &ddr2_data,
434                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
435 }
436 #endif
437
438 /*
439  * Basic board specific setup.  Pinmux has been handled already.
440  */
441 int board_init(void)
442 {
443 #if defined(CONFIG_HW_WATCHDOG)
444         hw_watchdog_init();
445 #endif
446
447         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
448 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
449         gpmc_init();
450 #endif
451         return 0;
452 }
453
454 #ifdef CONFIG_BOARD_LATE_INIT
455 int board_late_init(void)
456 {
457 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
458         int rc;
459         char *name = NULL;
460
461         rc = read_eeprom();
462         if (rc)
463                 puts("Could not get board ID.\n");
464
465         if (board_is_bbg1())
466                 name = "BBG1";
467         set_board_info_env(name);
468 #endif
469
470         return 0;
471 }
472 #endif
473
474 #ifndef CONFIG_DM_ETH
475
476 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
477         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
478 static void cpsw_control(int enabled)
479 {
480         /* VTP can be added here */
481
482         return;
483 }
484
485 static struct cpsw_slave_data cpsw_slaves[] = {
486         {
487                 .slave_reg_ofs  = 0x208,
488                 .sliver_reg_ofs = 0xd80,
489                 .phy_addr       = 0,
490         },
491         {
492                 .slave_reg_ofs  = 0x308,
493                 .sliver_reg_ofs = 0xdc0,
494                 .phy_addr       = 1,
495         },
496 };
497
498 static struct cpsw_platform_data cpsw_data = {
499         .mdio_base              = CPSW_MDIO_BASE,
500         .cpsw_base              = CPSW_BASE,
501         .mdio_div               = 0xff,
502         .channels               = 8,
503         .cpdma_reg_ofs          = 0x800,
504         .slaves                 = 1,
505         .slave_data             = cpsw_slaves,
506         .ale_reg_ofs            = 0xd00,
507         .ale_entries            = 1024,
508         .host_port_reg_ofs      = 0x108,
509         .hw_stats_reg_ofs       = 0x900,
510         .bd_ram_ofs             = 0x2000,
511         .mac_control            = (1 << 5),
512         .control                = cpsw_control,
513         .host_port_num          = 0,
514         .version                = CPSW_CTRL_VERSION_2,
515 };
516 #endif
517
518 /*
519  * This function will:
520  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
521  * in the environment
522  * Perform fixups to the PHY present on certain boards.  We only need this
523  * function in:
524  * - SPL with either CPSW or USB ethernet support
525  * - Full U-Boot, with either CPSW or USB ethernet
526  * Build in only these cases to avoid warnings about unused variables
527  * when we build an SPL that has neither option but full U-Boot will.
528  */
529 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
530                 && defined(CONFIG_SPL_BUILD)) || \
531         ((defined(CONFIG_DRIVER_TI_CPSW) || \
532           defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
533          !defined(CONFIG_SPL_BUILD))
534 int board_eth_init(bd_t *bis)
535 {
536         int rv, n = 0;
537         uint8_t mac_addr[6];
538         uint32_t mac_hi, mac_lo;
539         __maybe_unused struct ti_am_eeprom *header;
540
541         /* try reading mac address from efuse */
542         mac_lo = readl(&cdev->macid0l);
543         mac_hi = readl(&cdev->macid0h);
544         mac_addr[0] = mac_hi & 0xFF;
545         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
546         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
547         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
548         mac_addr[4] = mac_lo & 0xFF;
549         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
550
551 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
552         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
553         if (!getenv("ethaddr")) {
554                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
555
556                 if (is_valid_ethaddr(mac_addr))
557                         eth_setenv_enetaddr("ethaddr", mac_addr);
558         }
559
560 #ifdef CONFIG_DRIVER_TI_CPSW
561
562         mac_lo = readl(&cdev->macid1l);
563         mac_hi = readl(&cdev->macid1h);
564         mac_addr[0] = mac_hi & 0xFF;
565         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
566         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
567         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
568         mac_addr[4] = mac_lo & 0xFF;
569         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
570
571         if (!getenv("eth1addr")) {
572                 if (is_valid_ethaddr(mac_addr))
573                         eth_setenv_enetaddr("eth1addr", mac_addr);
574         }
575
576         if (read_eeprom() < 0)
577                 puts("Could not get board ID.\n");
578
579         if (board_is_bone() || board_is_bone_lt() ||
580             board_is_idk()) {
581                 writel(MII_MODE_ENABLE, &cdev->miisel);
582                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
583                                 PHY_INTERFACE_MODE_MII;
584         } else {
585                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
586                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
587                                 PHY_INTERFACE_MODE_RGMII;
588         }
589
590         rv = cpsw_register(&cpsw_data);
591         if (rv < 0)
592                 printf("Error %d registering CPSW switch\n", rv);
593         else
594                 n += rv;
595 #endif
596
597         /*
598          *
599          * CPSW RGMII Internal Delay Mode is not supported in all PVT
600          * operating points.  So we must set the TX clock delay feature
601          * in the AR8051 PHY.  Since we only support a single ethernet
602          * device in U-Boot, we only do this for the first instance.
603          */
604 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
605 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
606 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
607 #define AR8051_RGMII_TX_CLK_DLY         0x100
608
609         if (board_is_evm_sk() || board_is_gp_evm()) {
610                 const char *devname;
611                 devname = miiphy_get_current_dev();
612
613                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
614                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
615                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
616                                 AR8051_RGMII_TX_CLK_DLY);
617         }
618 #endif
619 #if defined(CONFIG_USB_ETHER) && \
620         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
621         if (is_valid_ethaddr(mac_addr))
622                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
623
624         rv = usb_eth_initialize(bis);
625         if (rv < 0)
626                 printf("Error %d registering USB_ETHER\n", rv);
627         else
628                 n += rv;
629 #endif
630         return n;
631 }
632 #endif
633
634 #endif /* CONFIG_DM_ETH */