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   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <spl.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/omap.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/io.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36 #include "board.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  41 #ifdef CONFIG_SPL_BUILD
  42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  43 #endif
  44
  45 /* MII mode defines */
  46 #define MII_MODE_ENABLE         0x0
  47 #define RGMII_MODE_ENABLE       0xA
  48
  49 /* GPIO that controls power to DDR on EVM-SK */
  50 #define GPIO_DDR_VTT_EN         7
  51
  52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  53
  54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  55
  56 static inline int board_is_bone(void)
  57 {
  58         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
  59 }
  60
  61 static inline int board_is_bone_lt(void)
  62 {
  63         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
  64 }
  65
  66 static inline int board_is_evm_sk(void)
  67 {
  68         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
  69 }
  70
  71 /*
  72  * Read header information from EEPROM into global structure.
  73  */
  74 static int read_eeprom(void)
  75 {
  76         /* Check if baseboard eeprom is available */
  77         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  78                 puts("Could not probe the EEPROM; something fundamentally "
  79                         "wrong on the I2C bus.\n");
  80                 return -ENODEV;
  81         }
  82
  83         /* read the eeprom using i2c */
  84         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  85                                                         sizeof(header))) {
  86                 puts("Could not read the EEPROM; something fundamentally"
  87                         " wrong on the I2C bus.\n");
  88                 return -EIO;
  89         }
  90
  91         if (header.magic != 0xEE3355AA) {
  92                 /*
  93                  * read the eeprom using i2c again,
  94                  * but use only a 1 byte address
  95                  */
  96                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
  97                                         (uchar *)&header, sizeof(header))) {
  98                         puts("Could not read the EEPROM; something "
  99                                 "fundamentally wrong on the I2C bus.\n");
 100                         return -EIO;
 101                 }
 102
 103                 if (header.magic != 0xEE3355AA) {
 104                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 105                                         header.magic);
 106                         return -EINVAL;
 107                 }
 108         }
 109
 110         return 0;
 111 }
 112
 113 /* UART Defines */
 114 #ifdef CONFIG_SPL_BUILD
 115 #define UART_RESET              (0x1 << 1)
 116 #define UART_CLK_RUNNING_MASK   0x1
 117 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 118
 119 static void rtc32k_enable(void)
 120 {
 121         struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
 122
 123         /*
 124          * Unlock the RTC's registers.  For more details please see the
 125          * RTC_SS section of the TRM.  In order to unlock we need to
 126          * write these specific values (keys) in this order.
 127          */
 128         writel(0x83e70b13, &rtc->kick0r);
 129         writel(0x95a4f1e0, &rtc->kick1r);
 130
 131         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
 132         writel((1 << 3) | (1 << 6), &rtc->osc);
 133 }
 134 #endif
 135
 136 /*
 137  * Determine what type of DDR we have.
 138  */
 139 static short inline board_memory_type(void)
 140 {
 141         /* The following boards are known to use DDR3. */
 142         if (board_is_evm_sk() || board_is_bone_lt())
 143                 return EMIF_REG_SDRAM_TYPE_DDR3;
 144
 145         return EMIF_REG_SDRAM_TYPE_DDR2;
 146 }
 147
 148 /*
 149  * early system init of muxing and clocks.
 150  */
 151 void s_init(void)
 152 {
 153         /* WDT1 is already running when the bootloader gets control
 154          * Disable it to avoid "random" resets
 155          */
 156         writel(0xAAAA, &wdtimer->wdtwspr);
 157         while (readl(&wdtimer->wdtwwps) != 0x0)
 158                 ;
 159         writel(0x5555, &wdtimer->wdtwspr);
 160         while (readl(&wdtimer->wdtwwps) != 0x0)
 161                 ;
 162
 163 #ifdef CONFIG_SPL_BUILD
 164         /* Setup the PLLs and the clocks for the peripherals */
 165         pll_init();
 166
 167         /* Enable RTC32K clock */
 168         rtc32k_enable();
 169
 170         /* UART softreset */
 171         u32 regVal;
 172
 173         enable_uart0_pin_mux();
 174
 175         regVal = readl(&uart_base->uartsyscfg);
 176         regVal |= UART_RESET;
 177         writel(regVal, &uart_base->uartsyscfg);
 178         while ((readl(&uart_base->uartsyssts) &
 179                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 180                 ;
 181
 182         /* Disable smart idle */
 183         regVal = readl(&uart_base->uartsyscfg);
 184         regVal |= UART_SMART_IDLE_EN;
 185         writel(regVal, &uart_base->uartsyscfg);
 186
 187         gd = &gdata;
 188
 189         preloader_console_init();
 190
 191         /* Initalize the board header */
 192         enable_i2c0_pin_mux();
 193         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 194         if (read_eeprom() < 0)
 195                 puts("Could not get board ID.\n");
 196
 197         enable_board_pin_mux(&header);
 198         if (board_is_evm_sk()) {
 199                 /*
 200                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 201                  * This is safe enough to do on older revs.
 202                  */
 203                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 204                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 205         }
 206
 207         config_ddr(board_memory_type());
 208 #endif
 209 }
 210
 211 /*
 212  * Basic board specific setup.  Pinmux has been handled already.
 213  */
 214 int board_init(void)
 215 {
 216         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 217         if (read_eeprom() < 0)
 218                 puts("Could not get board ID.\n");
 219
 220         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 221
 222         return 0;
 223 }
 224
 225 #ifdef CONFIG_DRIVER_TI_CPSW
 226 static void cpsw_control(int enabled)
 227 {
 228         /* VTP can be added here */
 229
 230         return;
 231 }
 232
 233 static struct cpsw_slave_data cpsw_slaves[] = {
 234         {
 235                 .slave_reg_ofs  = 0x208,
 236                 .sliver_reg_ofs = 0xd80,
 237                 .phy_id         = 0,
 238         },
 239         {
 240                 .slave_reg_ofs  = 0x308,
 241                 .sliver_reg_ofs = 0xdc0,
 242                 .phy_id         = 1,
 243         },
 244 };
 245
 246 static struct cpsw_platform_data cpsw_data = {
 247         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 248         .cpsw_base              = AM335X_CPSW_BASE,
 249         .mdio_div               = 0xff,
 250         .channels               = 8,
 251         .cpdma_reg_ofs          = 0x800,
 252         .slaves                 = 1,
 253         .slave_data             = cpsw_slaves,
 254         .ale_reg_ofs            = 0xd00,
 255         .ale_entries            = 1024,
 256         .host_port_reg_ofs      = 0x108,
 257         .hw_stats_reg_ofs       = 0x900,
 258         .mac_control            = (1 << 5),
 259         .control                = cpsw_control,
 260         .host_port_num          = 0,
 261         .version                = CPSW_CTRL_VERSION_2,
 262 };
 263
 264 int board_eth_init(bd_t *bis)
 265 {
 266         uint8_t mac_addr[6];
 267         uint32_t mac_hi, mac_lo;
 268
 269         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 270                 debug("<ethaddr> not set. Reading from E-fuse\n");
 271                 /* try reading mac address from efuse */
 272                 mac_lo = readl(&cdev->macid0l);
 273                 mac_hi = readl(&cdev->macid0h);
 274                 mac_addr[0] = mac_hi & 0xFF;
 275                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 276                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 277                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 278                 mac_addr[4] = mac_lo & 0xFF;
 279                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 280
 281                 if (is_valid_ether_addr(mac_addr))
 282                         eth_setenv_enetaddr("ethaddr", mac_addr);
 283                 else
 284                         return -1;
 285         }
 286
 287         if (board_is_bone() || board_is_bone_lt()) {
 288                 writel(MII_MODE_ENABLE, &cdev->miisel);
 289                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 290                                 PHY_INTERFACE_MODE_MII;
 291         } else {
 292                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 293                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 294                                 PHY_INTERFACE_MODE_RGMII;
 295         }
 296
 297         return cpsw_register(&cpsw_data);
 298 }
 299 #endif