4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
41 #ifdef CONFIG_SPL_BUILD
42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
45 /* MII mode defines */
46 #define MII_MODE_ENABLE 0x0
47 #define RGMII_MODE_ENABLE 0x3A
49 /* GPIO that controls power to DDR on EVM-SK */
50 #define GPIO_DDR_VTT_EN 7
52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
56 static inline int board_is_bone(void)
58 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
61 static inline int board_is_bone_lt(void)
63 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
66 static inline int board_is_evm_sk(void)
68 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
71 static inline int board_is_idk(void)
73 return !strncmp(header.config, "SKU#02", 6);
76 static int __maybe_unused board_is_gp_evm(void)
78 return !strncmp("A33515BB", header.name, 8);
81 int board_is_evm_15_or_later(void)
83 return (!strncmp("A33515BB", header.name, 8) &&
84 strncmp("1.5", header.version, 3) <= 0);
88 * Read header information from EEPROM into global structure.
90 static int read_eeprom(void)
92 /* Check if baseboard eeprom is available */
93 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
94 puts("Could not probe the EEPROM; something fundamentally "
95 "wrong on the I2C bus.\n");
99 /* read the eeprom using i2c */
100 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
102 puts("Could not read the EEPROM; something fundamentally"
103 " wrong on the I2C bus.\n");
107 if (header.magic != 0xEE3355AA) {
109 * read the eeprom using i2c again,
110 * but use only a 1 byte address
112 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
113 (uchar *)&header, sizeof(header))) {
114 puts("Could not read the EEPROM; something "
115 "fundamentally wrong on the I2C bus.\n");
119 if (header.magic != 0xEE3355AA) {
120 printf("Incorrect magic number (0x%x) in EEPROM\n",
130 #ifdef CONFIG_SPL_BUILD
131 #define UART_RESET (0x1 << 1)
132 #define UART_CLK_RUNNING_MASK 0x1
133 #define UART_SMART_IDLE_EN (0x1 << 0x3)
135 static void rtc32k_enable(void)
137 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
140 * Unlock the RTC's registers. For more details please see the
141 * RTC_SS section of the TRM. In order to unlock we need to
142 * write these specific values (keys) in this order.
144 writel(0x83e70b13, &rtc->kick0r);
145 writel(0x95a4f1e0, &rtc->kick1r);
147 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
148 writel((1 << 3) | (1 << 6), &rtc->osc);
151 static const struct ddr_data ddr2_data = {
152 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
153 (MT47H128M16RT25E_RD_DQS<<20) |
154 (MT47H128M16RT25E_RD_DQS<<10) |
155 (MT47H128M16RT25E_RD_DQS<<0)),
156 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
157 (MT47H128M16RT25E_WR_DQS<<20) |
158 (MT47H128M16RT25E_WR_DQS<<10) |
159 (MT47H128M16RT25E_WR_DQS<<0)),
160 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
161 (MT47H128M16RT25E_PHY_WRLVL<<20) |
162 (MT47H128M16RT25E_PHY_WRLVL<<10) |
163 (MT47H128M16RT25E_PHY_WRLVL<<0)),
164 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
165 (MT47H128M16RT25E_PHY_GATELVL<<20) |
166 (MT47H128M16RT25E_PHY_GATELVL<<10) |
167 (MT47H128M16RT25E_PHY_GATELVL<<0)),
168 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
169 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
170 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
171 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
172 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
173 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
174 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
175 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
176 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
177 .datadldiff0 = PHY_DLL_LOCK_DIFF,
180 static const struct cmd_control ddr2_cmd_ctrl_data = {
181 .cmd0csratio = MT47H128M16RT25E_RATIO,
182 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
183 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
185 .cmd1csratio = MT47H128M16RT25E_RATIO,
186 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
187 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
189 .cmd2csratio = MT47H128M16RT25E_RATIO,
190 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
191 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
194 static const struct emif_regs ddr2_emif_reg_data = {
195 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
196 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
197 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
198 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
199 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
200 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
203 static const struct ddr_data ddr3_data = {
204 .datardsratio0 = MT41J128MJT125_RD_DQS,
205 .datawdsratio0 = MT41J128MJT125_WR_DQS,
206 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
207 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
208 .datadldiff0 = PHY_DLL_LOCK_DIFF,
211 static const struct ddr_data ddr3_beagleblack_data = {
212 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
213 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
214 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
215 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
216 .datadldiff0 = PHY_DLL_LOCK_DIFF,
219 static const struct ddr_data ddr3_evm_data = {
220 .datardsratio0 = MT41J512M8RH125_RD_DQS,
221 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
222 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
223 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
224 .datadldiff0 = PHY_DLL_LOCK_DIFF,
227 static const struct cmd_control ddr3_cmd_ctrl_data = {
228 .cmd0csratio = MT41J128MJT125_RATIO,
229 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
230 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
232 .cmd1csratio = MT41J128MJT125_RATIO,
233 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
234 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
236 .cmd2csratio = MT41J128MJT125_RATIO,
237 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
238 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
241 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
242 .cmd0csratio = MT41K256M16HA125E_RATIO,
243 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
244 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
246 .cmd1csratio = MT41K256M16HA125E_RATIO,
247 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
248 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
250 .cmd2csratio = MT41K256M16HA125E_RATIO,
251 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
252 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
255 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
256 .cmd0csratio = MT41J512M8RH125_RATIO,
257 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
258 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
260 .cmd1csratio = MT41J512M8RH125_RATIO,
261 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
262 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
264 .cmd2csratio = MT41J512M8RH125_RATIO,
265 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
266 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
269 static struct emif_regs ddr3_emif_reg_data = {
270 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
271 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
272 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
273 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
274 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
275 .zq_config = MT41J128MJT125_ZQ_CFG,
276 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
280 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
281 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
282 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
283 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
284 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
285 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
286 .zq_config = MT41K256M16HA125E_ZQ_CFG,
287 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
290 static struct emif_regs ddr3_evm_emif_reg_data = {
291 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
292 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
293 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
294 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
295 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
296 .zq_config = MT41J512M8RH125_ZQ_CFG,
297 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
301 #ifdef CONFIG_SPL_OS_BOOT
302 int spl_start_uboot(void)
304 /* break into full u-boot on 'c' */
305 return (serial_tstc() && serial_getc() == 'c');
312 * early system init of muxing and clocks.
317 * Save the boot parameters passed from romcode.
318 * We cannot delay the saving further than this,
319 * to prevent overwrites.
321 #ifdef CONFIG_SPL_BUILD
322 save_omap_boot_params();
325 /* WDT1 is already running when the bootloader gets control
326 * Disable it to avoid "random" resets
328 writel(0xAAAA, &wdtimer->wdtwspr);
329 while (readl(&wdtimer->wdtwwps) != 0x0)
331 writel(0x5555, &wdtimer->wdtwspr);
332 while (readl(&wdtimer->wdtwwps) != 0x0)
335 #ifdef CONFIG_SPL_BUILD
336 /* Setup the PLLs and the clocks for the peripherals */
339 /* Enable RTC32K clock */
345 #ifdef CONFIG_SERIAL1
346 enable_uart0_pin_mux();
347 #endif /* CONFIG_SERIAL1 */
348 #ifdef CONFIG_SERIAL2
349 enable_uart1_pin_mux();
350 #endif /* CONFIG_SERIAL2 */
351 #ifdef CONFIG_SERIAL3
352 enable_uart2_pin_mux();
353 #endif /* CONFIG_SERIAL3 */
354 #ifdef CONFIG_SERIAL4
355 enable_uart3_pin_mux();
356 #endif /* CONFIG_SERIAL4 */
357 #ifdef CONFIG_SERIAL5
358 enable_uart4_pin_mux();
359 #endif /* CONFIG_SERIAL5 */
360 #ifdef CONFIG_SERIAL6
361 enable_uart5_pin_mux();
362 #endif /* CONFIG_SERIAL6 */
364 regVal = readl(&uart_base->uartsyscfg);
365 regVal |= UART_RESET;
366 writel(regVal, &uart_base->uartsyscfg);
367 while ((readl(&uart_base->uartsyssts) &
368 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
371 /* Disable smart idle */
372 regVal = readl(&uart_base->uartsyscfg);
373 regVal |= UART_SMART_IDLE_EN;
374 writel(regVal, &uart_base->uartsyscfg);
378 preloader_console_init();
380 /* Initalize the board header */
381 enable_i2c0_pin_mux();
382 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
383 if (read_eeprom() < 0)
384 puts("Could not get board ID.\n");
386 enable_board_pin_mux(&header);
387 if (board_is_evm_sk()) {
389 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
390 * This is safe enough to do on older revs.
392 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
393 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
396 if (board_is_evm_sk())
397 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
398 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
399 else if (board_is_bone_lt())
400 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
401 &ddr3_beagleblack_data,
402 &ddr3_beagleblack_cmd_ctrl_data,
403 &ddr3_beagleblack_emif_reg_data, 0);
404 else if (board_is_evm_15_or_later())
405 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
406 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
408 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
409 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
414 * Basic board specific setup. Pinmux has been handled already.
418 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
419 if (read_eeprom() < 0)
420 puts("Could not get board ID.\n");
422 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
429 #ifdef CONFIG_BOARD_LATE_INIT
430 int board_late_init(void)
432 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
433 char safe_string[HDR_NAME_LEN + 1];
435 /* Now set variables based on the header. */
436 strncpy(safe_string, (char *)header.name, sizeof(header.name));
437 safe_string[sizeof(header.name)] = 0;
438 setenv("board_name", safe_string);
440 strncpy(safe_string, (char *)header.version, sizeof(header.version));
441 safe_string[sizeof(header.version)] = 0;
442 setenv("board_rev", safe_string);
449 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
450 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
451 static void cpsw_control(int enabled)
453 /* VTP can be added here */
458 static struct cpsw_slave_data cpsw_slaves[] = {
460 .slave_reg_ofs = 0x208,
461 .sliver_reg_ofs = 0xd80,
465 .slave_reg_ofs = 0x308,
466 .sliver_reg_ofs = 0xdc0,
471 static struct cpsw_platform_data cpsw_data = {
472 .mdio_base = CPSW_MDIO_BASE,
473 .cpsw_base = CPSW_BASE,
476 .cpdma_reg_ofs = 0x800,
478 .slave_data = cpsw_slaves,
479 .ale_reg_ofs = 0xd00,
481 .host_port_reg_ofs = 0x108,
482 .hw_stats_reg_ofs = 0x900,
483 .mac_control = (1 << 5),
484 .control = cpsw_control,
486 .version = CPSW_CTRL_VERSION_2,
490 #if defined(CONFIG_DRIVER_TI_CPSW) || \
491 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
492 int board_eth_init(bd_t *bis)
496 uint32_t mac_hi, mac_lo;
498 /* try reading mac address from efuse */
499 mac_lo = readl(&cdev->macid0l);
500 mac_hi = readl(&cdev->macid0h);
501 mac_addr[0] = mac_hi & 0xFF;
502 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
503 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
504 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
505 mac_addr[4] = mac_lo & 0xFF;
506 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
508 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
509 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
510 if (!getenv("ethaddr")) {
511 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
513 if (is_valid_ether_addr(mac_addr))
514 eth_setenv_enetaddr("ethaddr", mac_addr);
517 #ifdef CONFIG_DRIVER_TI_CPSW
518 if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
519 writel(MII_MODE_ENABLE, &cdev->miisel);
520 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
521 PHY_INTERFACE_MODE_MII;
523 writel(RGMII_MODE_ENABLE, &cdev->miisel);
524 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
525 PHY_INTERFACE_MODE_RGMII;
528 rv = cpsw_register(&cpsw_data);
530 printf("Error %d registering CPSW switch\n", rv);
537 * CPSW RGMII Internal Delay Mode is not supported in all PVT
538 * operating points. So we must set the TX clock delay feature
539 * in the AR8051 PHY. Since we only support a single ethernet
540 * device in U-Boot, we only do this for the first instance.
542 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
543 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
544 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
545 #define AR8051_RGMII_TX_CLK_DLY 0x100
547 if (board_is_evm_sk() || board_is_gp_evm()) {
549 devname = miiphy_get_current_dev();
551 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
552 AR8051_DEBUG_RGMII_CLK_DLY_REG);
553 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
554 AR8051_RGMII_TX_CLK_DLY);
557 #if defined(CONFIG_USB_ETHER) && \
558 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
559 if (is_valid_ether_addr(mac_addr))
560 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
562 rv = usb_eth_initialize(bis);
564 printf("Error %d registering USB_ETHER\n", rv);