git.sur5r.net Git - u-boot/blob - board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/clk_synthesizer.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/mmc_host_def.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mem.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <power/tps65217.h>
  31 #include <power/tps65910.h>
  32 #include <environment.h>
  33 #include <watchdog.h>
  34 #include <environment.h>
  35 #include "../common/board_detect.h"
  36 #include "board.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 /* GPIO that controls power to DDR on EVM-SK */
  41 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  42 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  43 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  44 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  45 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  46 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  47 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  48
  49 #if defined(CONFIG_SPL_BUILD) || \
  50         (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
  51 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  52 #endif
  53
  54 /*
  55  * Read header information from EEPROM into global structure.
  56  */
  57 static inline int __maybe_unused read_eeprom(void)
  58 {
  59         return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
  60 }
  61
  62 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  63 static const struct ddr_data ddr2_data = {
  64         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  65         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  66         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  67 };
  68
  69 static const struct cmd_control ddr2_cmd_ctrl_data = {
  70         .cmd0csratio = MT47H128M16RT25E_RATIO,
  71
  72         .cmd1csratio = MT47H128M16RT25E_RATIO,
  73
  74         .cmd2csratio = MT47H128M16RT25E_RATIO,
  75 };
  76
  77 static const struct emif_regs ddr2_emif_reg_data = {
  78         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  79         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  80         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  81         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  82         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  83         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  84 };
  85
  86 static const struct ddr_data ddr3_data = {
  87         .datardsratio0 = MT41J128MJT125_RD_DQS,
  88         .datawdsratio0 = MT41J128MJT125_WR_DQS,
  89         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  90         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  91 };
  92
  93 static const struct ddr_data ddr3_beagleblack_data = {
  94         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  95         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  96         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  97         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  98 };
  99
 100 static const struct ddr_data ddr3_evm_data = {
 101         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 102         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 103         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 104         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 105 };
 106
 107 static const struct ddr_data ddr3_icev2_data = {
 108         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 109         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 110         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 111         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 112 };
 113
 114 static const struct cmd_control ddr3_cmd_ctrl_data = {
 115         .cmd0csratio = MT41J128MJT125_RATIO,
 116         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 117
 118         .cmd1csratio = MT41J128MJT125_RATIO,
 119         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 120
 121         .cmd2csratio = MT41J128MJT125_RATIO,
 122         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 123 };
 124
 125 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 126         .cmd0csratio = MT41K256M16HA125E_RATIO,
 127         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 128
 129         .cmd1csratio = MT41K256M16HA125E_RATIO,
 130         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 131
 132         .cmd2csratio = MT41K256M16HA125E_RATIO,
 133         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 134 };
 135
 136 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 137         .cmd0csratio = MT41J512M8RH125_RATIO,
 138         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 139
 140         .cmd1csratio = MT41J512M8RH125_RATIO,
 141         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 142
 143         .cmd2csratio = MT41J512M8RH125_RATIO,
 144         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 145 };
 146
 147 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 148         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 149         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 150
 151         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 152         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 153
 154         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 155         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 156 };
 157
 158 static struct emif_regs ddr3_emif_reg_data = {
 159         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 160         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 161         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 162         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 163         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 164         .zq_config = MT41J128MJT125_ZQ_CFG,
 165         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 166                                 PHY_EN_DYN_PWRDN,
 167 };
 168
 169 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 170         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 171         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 172         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 173         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 174         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 175         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 176         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 177 };
 178
 179 static struct emif_regs ddr3_evm_emif_reg_data = {
 180         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 181         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 182         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 183         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 184         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 185         .zq_config = MT41J512M8RH125_ZQ_CFG,
 186         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 187                                 PHY_EN_DYN_PWRDN,
 188 };
 189
 190 static struct emif_regs ddr3_icev2_emif_reg_data = {
 191         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 192         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 193         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 194         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 195         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 196         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 197         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 198                                 PHY_EN_DYN_PWRDN,
 199 };
 200
 201 #ifdef CONFIG_SPL_OS_BOOT
 202 int spl_start_uboot(void)
 203 {
 204         /* break into full u-boot on 'c' */
 205         if (serial_tstc() && serial_getc() == 'c')
 206                 return 1;
 207
 208 #ifdef CONFIG_SPL_ENV_SUPPORT
 209         env_init();
 210         env_relocate_spec();
 211         if (getenv_yesno("boot_os") != 1)
 212                 return 1;
 213 #endif
 214
 215         return 0;
 216 }
 217 #endif
 218
 219 #define OSC     (V_OSCK/1000000)
 220 const struct dpll_params dpll_ddr = {
 221                 266, OSC-1, 1, -1, -1, -1, -1};
 222 const struct dpll_params dpll_ddr_evm_sk = {
 223                 303, OSC-1, 1, -1, -1, -1, -1};
 224 const struct dpll_params dpll_ddr_bone_black = {
 225                 400, OSC-1, 1, -1, -1, -1, -1};
 226
 227 void am33xx_spl_board_init(void)
 228 {
 229         int mpu_vdd;
 230
 231         if (read_eeprom() < 0)
 232                 puts("Could not get board ID.\n");
 233
 234         /* Get the frequency */
 235         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 236
 237         if (board_is_bone() || board_is_bone_lt()) {
 238                 /* BeagleBone PMIC Code */
 239                 int usb_cur_lim;
 240
 241                 /*
 242                  * Only perform PMIC configurations if board rev > A1
 243                  * on Beaglebone White
 244                  */
 245                 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 246                         return;
 247
 248                 if (i2c_probe(TPS65217_CHIP_PM))
 249                         return;
 250
 251                 /*
 252                  * On Beaglebone White we need to ensure we have AC power
 253                  * before increasing the frequency.
 254                  */
 255                 if (board_is_bone()) {
 256                         uchar pmic_status_reg;
 257                         if (tps65217_reg_read(TPS65217_STATUS,
 258                                               &pmic_status_reg))
 259                                 return;
 260                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 261                                 puts("No AC power, disabling frequency switch\n");
 262                                 return;
 263                         }
 264                 }
 265
 266                 /*
 267                  * Override what we have detected since we know if we have
 268                  * a Beaglebone Black it supports 1GHz.
 269                  */
 270                 if (board_is_bone_lt())
 271                         dpll_mpu_opp100.m = MPUPLL_M_1000;
 272
 273                 /*
 274                  * Increase USB current limit to 1300mA or 1800mA and set
 275                  * the MPU voltage controller as needed.
 276                  */
 277                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 278                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 279                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 280                 } else {
 281                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 282                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 283                 }
 284
 285                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 286                                        TPS65217_POWER_PATH,
 287                                        usb_cur_lim,
 288                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 289                         puts("tps65217_reg_write failure\n");
 290
 291                 /* Set DCDC3 (CORE) voltage to 1.125V */
 292                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 293                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
 294                         puts("tps65217_voltage_update failure\n");
 295                         return;
 296                 }
 297
 298                 /* Set CORE Frequencies to OPP100 */
 299                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 300
 301                 /* Set DCDC2 (MPU) voltage */
 302                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 303                         puts("tps65217_voltage_update failure\n");
 304                         return;
 305                 }
 306
 307                 /*
 308                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 309                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 310                  */
 311                 if (board_is_bone()) {
 312                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 313                                                TPS65217_DEFLS1,
 314                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 315                                                TPS65217_LDO_MASK))
 316                                 puts("tps65217_reg_write failure\n");
 317                 } else {
 318                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 319                                                TPS65217_DEFLS1,
 320                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 321                                                TPS65217_LDO_MASK))
 322                                 puts("tps65217_reg_write failure\n");
 323                 }
 324
 325                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 326                                        TPS65217_DEFLS2,
 327                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 328                                        TPS65217_LDO_MASK))
 329                         puts("tps65217_reg_write failure\n");
 330         } else {
 331                 int sil_rev;
 332
 333                 /*
 334                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 335                  * MPU frequencies we support we use a CORE voltage of
 336                  * 1.1375V.  For MPU voltage we need to switch based on
 337                  * the frequency we are running at.
 338                  */
 339                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 340                         return;
 341
 342                 /*
 343                  * Depending on MPU clock and PG we will need a different
 344                  * VDD to drive at that speed.
 345                  */
 346                 sil_rev = readl(&cdev->deviceid) >> 28;
 347                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 348                                                       dpll_mpu_opp100.m);
 349
 350                 /* Tell the TPS65910 to use i2c */
 351                 tps65910_set_i2c_control();
 352
 353                 /* First update MPU voltage. */
 354                 if (tps65910_voltage_update(MPU, mpu_vdd))
 355                         return;
 356
 357                 /* Second, update the CORE voltage. */
 358                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 359                         return;
 360
 361                 /* Set CORE Frequencies to OPP100 */
 362                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 363         }
 364
 365         /* Set MPU Frequency to what we detected now that voltages are set */
 366         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 367 }
 368
 369 const struct dpll_params *get_dpll_ddr_params(void)
 370 {
 371         enable_i2c0_pin_mux();
 372         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 373         if (read_eeprom() < 0)
 374                 puts("Could not get board ID.\n");
 375
 376         if (board_is_evm_sk())
 377                 return &dpll_ddr_evm_sk;
 378         else if (board_is_bone_lt() || board_is_icev2())
 379                 return &dpll_ddr_bone_black;
 380         else if (board_is_evm_15_or_later())
 381                 return &dpll_ddr_evm_sk;
 382         else
 383                 return &dpll_ddr;
 384 }
 385
 386 void set_uart_mux_conf(void)
 387 {
 388 #if CONFIG_CONS_INDEX == 1
 389         enable_uart0_pin_mux();
 390 #elif CONFIG_CONS_INDEX == 2
 391         enable_uart1_pin_mux();
 392 #elif CONFIG_CONS_INDEX == 3
 393         enable_uart2_pin_mux();
 394 #elif CONFIG_CONS_INDEX == 4
 395         enable_uart3_pin_mux();
 396 #elif CONFIG_CONS_INDEX == 5
 397         enable_uart4_pin_mux();
 398 #elif CONFIG_CONS_INDEX == 6
 399         enable_uart5_pin_mux();
 400 #endif
 401 }
 402
 403 void set_mux_conf_regs(void)
 404 {
 405         if (read_eeprom() < 0)
 406                 puts("Could not get board ID.\n");
 407
 408         enable_board_pin_mux();
 409 }
 410
 411 const struct ctrl_ioregs ioregs_evmsk = {
 412         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 413         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 414         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 415         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 416         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 417 };
 418
 419 const struct ctrl_ioregs ioregs_bonelt = {
 420         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 421         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 422         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 423         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 424         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 425 };
 426
 427 const struct ctrl_ioregs ioregs_evm15 = {
 428         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 429         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 430         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 431         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 432         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 433 };
 434
 435 const struct ctrl_ioregs ioregs = {
 436         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 437         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 438         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 439         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 440         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 441 };
 442
 443 void sdram_init(void)
 444 {
 445         if (read_eeprom() < 0)
 446                 puts("Could not get board ID.\n");
 447
 448         if (board_is_evm_sk()) {
 449                 /*
 450                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 451                  * This is safe enough to do on older revs.
 452                  */
 453                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 454                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 455         }
 456
 457         if (board_is_icev2()) {
 458                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 459                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 460         }
 461
 462         if (board_is_evm_sk())
 463                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 464                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 465         else if (board_is_bone_lt())
 466                 config_ddr(400, &ioregs_bonelt,
 467                            &ddr3_beagleblack_data,
 468                            &ddr3_beagleblack_cmd_ctrl_data,
 469                            &ddr3_beagleblack_emif_reg_data, 0);
 470         else if (board_is_evm_15_or_later())
 471                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 472                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 473         else if (board_is_icev2())
 474                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 475                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 476                            0);
 477         else
 478                 config_ddr(266, &ioregs, &ddr2_data,
 479                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 480 }
 481 #endif
 482
 483 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 484         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 485 static void request_and_set_gpio(int gpio, char *name)
 486 {
 487         int ret;
 488
 489         ret = gpio_request(gpio, name);
 490         if (ret < 0) {
 491                 printf("%s: Unable to request %s\n", __func__, name);
 492                 return;
 493         }
 494
 495         ret = gpio_direction_output(gpio, 0);
 496         if (ret < 0) {
 497                 printf("%s: Unable to set %s  as output\n", __func__, name);
 498                 goto err_free_gpio;
 499         }
 500
 501         gpio_set_value(gpio, 1);
 502
 503         return;
 504
 505 err_free_gpio:
 506         gpio_free(gpio);
 507 }
 508
 509 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N);
 510
 511 /**
 512  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 513  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 514  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 515  * give 50MHz output for Eth0 and 1.
 516  */
 517 static struct clk_synth cdce913_data = {
 518         .id = 0x81,
 519         .capacitor = 0x90,
 520         .mux = 0x6d,
 521         .pdiv2 = 0x2,
 522         .pdiv3 = 0x2,
 523 };
 524 #endif
 525
 526 /*
 527  * Basic board specific setup.  Pinmux has been handled already.
 528  */
 529 int board_init(void)
 530 {
 531 #if defined(CONFIG_HW_WATCHDOG)
 532         hw_watchdog_init();
 533 #endif
 534
 535         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 536 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 537         gpmc_init();
 538 #endif
 539 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
 540         int rv;
 541
 542         if (board_is_icev2()) {
 543                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 544                 REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
 545                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 546                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 547
 548                 rv = setup_clock_synthesizer(&cdce913_data);
 549                 if (rv) {
 550                         printf("Clock synthesizer setup failed %d\n", rv);
 551                         return rv;
 552                 }
 553         }
 554 #endif
 555
 556         return 0;
 557 }
 558
 559 #ifdef CONFIG_BOARD_LATE_INIT
 560 int board_late_init(void)
 561 {
 562 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 563         int rc;
 564         char *name = NULL;
 565
 566         rc = read_eeprom();
 567         if (rc)
 568                 puts("Could not get board ID.\n");
 569
 570         if (board_is_bbg1())
 571                 name = "BBG1";
 572         set_board_info_env(name);
 573 #endif
 574
 575         return 0;
 576 }
 577 #endif
 578
 579 #ifndef CONFIG_DM_ETH
 580
 581 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 582         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 583 static void cpsw_control(int enabled)
 584 {
 585         /* VTP can be added here */
 586
 587         return;
 588 }
 589
 590 static struct cpsw_slave_data cpsw_slaves[] = {
 591         {
 592                 .slave_reg_ofs  = 0x208,
 593                 .sliver_reg_ofs = 0xd80,
 594                 .phy_addr       = 0,
 595         },
 596         {
 597                 .slave_reg_ofs  = 0x308,
 598                 .sliver_reg_ofs = 0xdc0,
 599                 .phy_addr       = 1,
 600         },
 601 };
 602
 603 static struct cpsw_platform_data cpsw_data = {
 604         .mdio_base              = CPSW_MDIO_BASE,
 605         .cpsw_base              = CPSW_BASE,
 606         .mdio_div               = 0xff,
 607         .channels               = 8,
 608         .cpdma_reg_ofs          = 0x800,
 609         .slaves                 = 1,
 610         .slave_data             = cpsw_slaves,
 611         .ale_reg_ofs            = 0xd00,
 612         .ale_entries            = 1024,
 613         .host_port_reg_ofs      = 0x108,
 614         .hw_stats_reg_ofs       = 0x900,
 615         .bd_ram_ofs             = 0x2000,
 616         .mac_control            = (1 << 5),
 617         .control                = cpsw_control,
 618         .host_port_num          = 0,
 619         .version                = CPSW_CTRL_VERSION_2,
 620 };
 621 #endif
 622
 623 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
 624         defined(CONFIG_SPL_BUILD)) || \
 625         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 626           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 627          !defined(CONFIG_SPL_BUILD))
 628
 629 /*
 630  * This function will:
 631  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 632  * in the environment
 633  * Perform fixups to the PHY present on certain boards.  We only need this
 634  * function in:
 635  * - SPL with either CPSW or USB ethernet support
 636  * - Full U-Boot, with either CPSW or USB ethernet
 637  * Build in only these cases to avoid warnings about unused variables
 638  * when we build an SPL that has neither option but full U-Boot will.
 639  */
 640 int board_eth_init(bd_t *bis)
 641 {
 642         int rv, n = 0;
 643         uint8_t mac_addr[6];
 644         uint32_t mac_hi, mac_lo;
 645         __maybe_unused struct ti_am_eeprom *header;
 646
 647         /* try reading mac address from efuse */
 648         mac_lo = readl(&cdev->macid0l);
 649         mac_hi = readl(&cdev->macid0h);
 650         mac_addr[0] = mac_hi & 0xFF;
 651         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 652         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 653         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 654         mac_addr[4] = mac_lo & 0xFF;
 655         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 656
 657 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 658         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 659         if (!getenv("ethaddr")) {
 660                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 661
 662                 if (is_valid_ethaddr(mac_addr))
 663                         eth_setenv_enetaddr("ethaddr", mac_addr);
 664         }
 665
 666 #ifdef CONFIG_DRIVER_TI_CPSW
 667
 668         mac_lo = readl(&cdev->macid1l);
 669         mac_hi = readl(&cdev->macid1h);
 670         mac_addr[0] = mac_hi & 0xFF;
 671         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 672         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 673         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 674         mac_addr[4] = mac_lo & 0xFF;
 675         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 676
 677         if (!getenv("eth1addr")) {
 678                 if (is_valid_ethaddr(mac_addr))
 679                         eth_setenv_enetaddr("eth1addr", mac_addr);
 680         }
 681
 682         if (read_eeprom() < 0)
 683                 puts("Could not get board ID.\n");
 684
 685         if (board_is_bone() || board_is_bone_lt() ||
 686             board_is_idk()) {
 687                 writel(MII_MODE_ENABLE, &cdev->miisel);
 688                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 689                                 PHY_INTERFACE_MODE_MII;
 690         } else if (board_is_icev2()) {
 691                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 692                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 693                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
 694                 cpsw_slaves[0].phy_addr = 1;
 695                 cpsw_slaves[1].phy_addr = 3;
 696         } else {
 697                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 698                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 699                                 PHY_INTERFACE_MODE_RGMII;
 700         }
 701
 702         rv = cpsw_register(&cpsw_data);
 703         if (rv < 0)
 704                 printf("Error %d registering CPSW switch\n", rv);
 705         else
 706                 n += rv;
 707 #endif
 708
 709         /*
 710          *
 711          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 712          * operating points.  So we must set the TX clock delay feature
 713          * in the AR8051 PHY.  Since we only support a single ethernet
 714          * device in U-Boot, we only do this for the first instance.
 715          */
 716 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 717 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 718 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 719 #define AR8051_RGMII_TX_CLK_DLY         0x100
 720
 721         if (board_is_evm_sk() || board_is_gp_evm()) {
 722                 const char *devname;
 723                 devname = miiphy_get_current_dev();
 724
 725                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 726                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 727                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 728                                 AR8051_RGMII_TX_CLK_DLY);
 729         }
 730 #endif
 731 #if defined(CONFIG_USB_ETHER) && \
 732         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 733         if (is_valid_ethaddr(mac_addr))
 734                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 735
 736         rv = usb_eth_initialize(bis);
 737         if (rv < 0)
 738                 printf("Error %d registering USB_ETHER\n", rv);
 739         else
 740                 n += rv;
 741 #endif
 742         return n;
 743 }
 744 #endif
 745
 746 #endif /* CONFIG_DM_ETH */
 747
 748 #ifdef CONFIG_SPL_LOAD_FIT
 749 int board_fit_config_name_match(const char *name)
 750 {
 751         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 752                 return 0;
 753         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 754                 return 0;
 755         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 756                 return 0;
 757         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 758                 return 0;
 759         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 760                 return 0;
 761         else
 762                 return -1;
 763 }
 764 #endif