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1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <errno.h>
13 #include <spl.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include <asm/io.h>
24 #include <asm/emif.h>
25 #include <asm/gpio.h>
26 #include <i2c.h>
27 #include <miiphy.h>
28 #include <cpsw.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
31 #include <environment.h>
32 #include <watchdog.h>
33 #include <environment.h>
34 #include "board.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN         7
40
41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
42
43 /*
44  * Read header information from EEPROM into global structure.
45  */
46 static int read_eeprom(struct am335x_baseboard_id *header)
47 {
48         /* Check if baseboard eeprom is available */
49         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
50                 puts("Could not probe the EEPROM; something fundamentally "
51                         "wrong on the I2C bus.\n");
52                 return -ENODEV;
53         }
54
55         /* read the eeprom using i2c */
56         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
57                      sizeof(struct am335x_baseboard_id))) {
58                 puts("Could not read the EEPROM; something fundamentally"
59                         " wrong on the I2C bus.\n");
60                 return -EIO;
61         }
62
63         if (header->magic != 0xEE3355AA) {
64                 /*
65                  * read the eeprom using i2c again,
66                  * but use only a 1 byte address
67                  */
68                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
69                              sizeof(struct am335x_baseboard_id))) {
70                         puts("Could not read the EEPROM; something "
71                                 "fundamentally wrong on the I2C bus.\n");
72                         return -EIO;
73                 }
74
75                 if (header->magic != 0xEE3355AA) {
76                         printf("Incorrect magic number (0x%x) in EEPROM\n",
77                                         header->magic);
78                         return -EINVAL;
79                 }
80         }
81
82         return 0;
83 }
84
85 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
86 static const struct ddr_data ddr2_data = {
87         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
88         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
89         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
90 };
91
92 static const struct cmd_control ddr2_cmd_ctrl_data = {
93         .cmd0csratio = MT47H128M16RT25E_RATIO,
94
95         .cmd1csratio = MT47H128M16RT25E_RATIO,
96
97         .cmd2csratio = MT47H128M16RT25E_RATIO,
98 };
99
100 static const struct emif_regs ddr2_emif_reg_data = {
101         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
102         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
103         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
104         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
105         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
106         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
107 };
108
109 static const struct ddr_data ddr3_data = {
110         .datardsratio0 = MT41J128MJT125_RD_DQS,
111         .datawdsratio0 = MT41J128MJT125_WR_DQS,
112         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
113         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
114 };
115
116 static const struct ddr_data ddr3_beagleblack_data = {
117         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
118         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
119         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
120         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
121 };
122
123 static const struct ddr_data ddr3_evm_data = {
124         .datardsratio0 = MT41J512M8RH125_RD_DQS,
125         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
126         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
127         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
128 };
129
130 static const struct cmd_control ddr3_cmd_ctrl_data = {
131         .cmd0csratio = MT41J128MJT125_RATIO,
132         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
133
134         .cmd1csratio = MT41J128MJT125_RATIO,
135         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
136
137         .cmd2csratio = MT41J128MJT125_RATIO,
138         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
139 };
140
141 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
142         .cmd0csratio = MT41K256M16HA125E_RATIO,
143         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
144
145         .cmd1csratio = MT41K256M16HA125E_RATIO,
146         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
147
148         .cmd2csratio = MT41K256M16HA125E_RATIO,
149         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
150 };
151
152 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
153         .cmd0csratio = MT41J512M8RH125_RATIO,
154         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
155
156         .cmd1csratio = MT41J512M8RH125_RATIO,
157         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
158
159         .cmd2csratio = MT41J512M8RH125_RATIO,
160         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
161 };
162
163 static struct emif_regs ddr3_emif_reg_data = {
164         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
165         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
166         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
167         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
168         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
169         .zq_config = MT41J128MJT125_ZQ_CFG,
170         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
171                                 PHY_EN_DYN_PWRDN,
172 };
173
174 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
175         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
176         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
177         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
178         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
179         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
180         .zq_config = MT41K256M16HA125E_ZQ_CFG,
181         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
182 };
183
184 static struct emif_regs ddr3_evm_emif_reg_data = {
185         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
186         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
187         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
188         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
189         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
190         .zq_config = MT41J512M8RH125_ZQ_CFG,
191         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
192                                 PHY_EN_DYN_PWRDN,
193 };
194
195 #ifdef CONFIG_SPL_OS_BOOT
196 int spl_start_uboot(void)
197 {
198         /* break into full u-boot on 'c' */
199         if (serial_tstc() && serial_getc() == 'c')
200                 return 1;
201
202 #ifdef CONFIG_SPL_ENV_SUPPORT
203         env_init();
204         env_relocate_spec();
205         if (getenv_yesno("boot_os") != 1)
206                 return 1;
207 #endif
208
209         return 0;
210 }
211 #endif
212
213 #define OSC     (V_OSCK/1000000)
214 const struct dpll_params dpll_ddr = {
215                 266, OSC-1, 1, -1, -1, -1, -1};
216 const struct dpll_params dpll_ddr_evm_sk = {
217                 303, OSC-1, 1, -1, -1, -1, -1};
218 const struct dpll_params dpll_ddr_bone_black = {
219                 400, OSC-1, 1, -1, -1, -1, -1};
220
221 void am33xx_spl_board_init(void)
222 {
223         struct am335x_baseboard_id header;
224         int mpu_vdd;
225
226         if (read_eeprom(&header) < 0)
227                 puts("Could not get board ID.\n");
228
229         /* Get the frequency */
230         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
231
232         if (board_is_bone(&header) || board_is_bone_lt(&header)) {
233                 /* BeagleBone PMIC Code */
234                 int usb_cur_lim;
235
236                 /*
237                  * Only perform PMIC configurations if board rev > A1
238                  * on Beaglebone White
239                  */
240                 if (board_is_bone(&header) && !strncmp(header.version,
241                                                        "00A1", 4))
242                         return;
243
244                 if (i2c_probe(TPS65217_CHIP_PM))
245                         return;
246
247                 /*
248                  * On Beaglebone White we need to ensure we have AC power
249                  * before increasing the frequency.
250                  */
251                 if (board_is_bone(&header)) {
252                         uchar pmic_status_reg;
253                         if (tps65217_reg_read(TPS65217_STATUS,
254                                               &pmic_status_reg))
255                                 return;
256                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
257                                 puts("No AC power, disabling frequency switch\n");
258                                 return;
259                         }
260                 }
261
262                 /*
263                  * Override what we have detected since we know if we have
264                  * a Beaglebone Black it supports 1GHz.
265                  */
266                 if (board_is_bone_lt(&header))
267                         dpll_mpu_opp100.m = MPUPLL_M_1000;
268
269                 /*
270                  * Increase USB current limit to 1300mA or 1800mA and set
271                  * the MPU voltage controller as needed.
272                  */
273                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
274                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
275                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
276                 } else {
277                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
278                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
279                 }
280
281                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
282                                        TPS65217_POWER_PATH,
283                                        usb_cur_lim,
284                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
285                         puts("tps65217_reg_write failure\n");
286
287                 /* Set DCDC3 (CORE) voltage to 1.125V */
288                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
289                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
290                         puts("tps65217_voltage_update failure\n");
291                         return;
292                 }
293
294                 /* Set CORE Frequencies to OPP100 */
295                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
296
297                 /* Set DCDC2 (MPU) voltage */
298                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
299                         puts("tps65217_voltage_update failure\n");
300                         return;
301                 }
302
303                 /*
304                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
305                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
306                  */
307                 if (board_is_bone(&header)) {
308                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
309                                                TPS65217_DEFLS1,
310                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
311                                                TPS65217_LDO_MASK))
312                                 puts("tps65217_reg_write failure\n");
313                 } else {
314                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
315                                                TPS65217_DEFLS1,
316                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
317                                                TPS65217_LDO_MASK))
318                                 puts("tps65217_reg_write failure\n");
319                 }
320
321                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
322                                        TPS65217_DEFLS2,
323                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
324                                        TPS65217_LDO_MASK))
325                         puts("tps65217_reg_write failure\n");
326         } else {
327                 int sil_rev;
328
329                 /*
330                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
331                  * MPU frequencies we support we use a CORE voltage of
332                  * 1.1375V.  For MPU voltage we need to switch based on
333                  * the frequency we are running at.
334                  */
335                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
336                         return;
337
338                 /*
339                  * Depending on MPU clock and PG we will need a different
340                  * VDD to drive at that speed.
341                  */
342                 sil_rev = readl(&cdev->deviceid) >> 28;
343                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
344                                                       dpll_mpu_opp100.m);
345
346                 /* Tell the TPS65910 to use i2c */
347                 tps65910_set_i2c_control();
348
349                 /* First update MPU voltage. */
350                 if (tps65910_voltage_update(MPU, mpu_vdd))
351                         return;
352
353                 /* Second, update the CORE voltage. */
354                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
355                         return;
356
357                 /* Set CORE Frequencies to OPP100 */
358                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
359         }
360
361         /* Set MPU Frequency to what we detected now that voltages are set */
362         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
363 }
364
365 const struct dpll_params *get_dpll_ddr_params(void)
366 {
367         struct am335x_baseboard_id header;
368
369         enable_i2c0_pin_mux();
370         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
371         if (read_eeprom(&header) < 0)
372                 puts("Could not get board ID.\n");
373
374         if (board_is_evm_sk(&header))
375                 return &dpll_ddr_evm_sk;
376         else if (board_is_bone_lt(&header))
377                 return &dpll_ddr_bone_black;
378         else if (board_is_evm_15_or_later(&header))
379                 return &dpll_ddr_evm_sk;
380         else
381                 return &dpll_ddr;
382 }
383
384 void set_uart_mux_conf(void)
385 {
386 #if CONFIG_CONS_INDEX == 1
387         enable_uart0_pin_mux();
388 #elif CONFIG_CONS_INDEX == 2
389         enable_uart1_pin_mux();
390 #elif CONFIG_CONS_INDEX == 3
391         enable_uart2_pin_mux();
392 #elif CONFIG_CONS_INDEX == 4
393         enable_uart3_pin_mux();
394 #elif CONFIG_CONS_INDEX == 5
395         enable_uart4_pin_mux();
396 #elif CONFIG_CONS_INDEX == 6
397         enable_uart5_pin_mux();
398 #endif
399 }
400
401 void set_mux_conf_regs(void)
402 {
403         __maybe_unused struct am335x_baseboard_id header;
404
405         if (read_eeprom(&header) < 0)
406                 puts("Could not get board ID.\n");
407
408         enable_board_pin_mux(&header);
409 }
410
411 const struct ctrl_ioregs ioregs_evmsk = {
412         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
413         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
414         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
415         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
416         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
417 };
418
419 const struct ctrl_ioregs ioregs_bonelt = {
420         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
421         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
422         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
423         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
424         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
425 };
426
427 const struct ctrl_ioregs ioregs_evm15 = {
428         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
429         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
430         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
431         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
432         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
433 };
434
435 const struct ctrl_ioregs ioregs = {
436         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
437         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
438         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
439         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
440         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
441 };
442
443 void sdram_init(void)
444 {
445         __maybe_unused struct am335x_baseboard_id header;
446
447         if (read_eeprom(&header) < 0)
448                 puts("Could not get board ID.\n");
449
450         if (board_is_evm_sk(&header)) {
451                 /*
452                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
453                  * This is safe enough to do on older revs.
454                  */
455                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
456                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
457         }
458
459         if (board_is_evm_sk(&header))
460                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
461                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
462         else if (board_is_bone_lt(&header))
463                 config_ddr(400, &ioregs_bonelt,
464                            &ddr3_beagleblack_data,
465                            &ddr3_beagleblack_cmd_ctrl_data,
466                            &ddr3_beagleblack_emif_reg_data, 0);
467         else if (board_is_evm_15_or_later(&header))
468                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
469                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
470         else
471                 config_ddr(266, &ioregs, &ddr2_data,
472                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
473 }
474 #endif
475
476 /*
477  * Basic board specific setup.  Pinmux has been handled already.
478  */
479 int board_init(void)
480 {
481 #if defined(CONFIG_HW_WATCHDOG)
482         hw_watchdog_init();
483 #endif
484
485         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
486 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
487         gpmc_init();
488 #endif
489         return 0;
490 }
491
492 #ifdef CONFIG_BOARD_LATE_INIT
493 int board_late_init(void)
494 {
495 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
496         char safe_string[HDR_NAME_LEN + 1];
497         struct am335x_baseboard_id header;
498
499         if (read_eeprom(&header) < 0)
500                 puts("Could not get board ID.\n");
501
502         /* Now set variables based on the header. */
503         strncpy(safe_string, (char *)header.name, sizeof(header.name));
504         safe_string[sizeof(header.name)] = 0;
505         setenv("board_name", safe_string);
506
507         strncpy(safe_string, (char *)header.version, sizeof(header.version));
508         safe_string[sizeof(header.version)] = 0;
509         setenv("board_rev", safe_string);
510 #endif
511
512         return 0;
513 }
514 #endif
515
516 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
517         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
518 static void cpsw_control(int enabled)
519 {
520         /* VTP can be added here */
521
522         return;
523 }
524
525 static struct cpsw_slave_data cpsw_slaves[] = {
526         {
527                 .slave_reg_ofs  = 0x208,
528                 .sliver_reg_ofs = 0xd80,
529                 .phy_addr       = 0,
530         },
531         {
532                 .slave_reg_ofs  = 0x308,
533                 .sliver_reg_ofs = 0xdc0,
534                 .phy_addr       = 1,
535         },
536 };
537
538 static struct cpsw_platform_data cpsw_data = {
539         .mdio_base              = CPSW_MDIO_BASE,
540         .cpsw_base              = CPSW_BASE,
541         .mdio_div               = 0xff,
542         .channels               = 8,
543         .cpdma_reg_ofs          = 0x800,
544         .slaves                 = 1,
545         .slave_data             = cpsw_slaves,
546         .ale_reg_ofs            = 0xd00,
547         .ale_entries            = 1024,
548         .host_port_reg_ofs      = 0x108,
549         .hw_stats_reg_ofs       = 0x900,
550         .bd_ram_ofs             = 0x2000,
551         .mac_control            = (1 << 5),
552         .control                = cpsw_control,
553         .host_port_num          = 0,
554         .version                = CPSW_CTRL_VERSION_2,
555 };
556 #endif
557
558 /*
559  * This function will:
560  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
561  * in the environment
562  * Perform fixups to the PHY present on certain boards.  We only need this
563  * function in:
564  * - SPL with either CPSW or USB ethernet support
565  * - Full U-Boot, with either CPSW or USB ethernet
566  * Build in only these cases to avoid warnings about unused variables
567  * when we build an SPL that has neither option but full U-Boot will.
568  */
569 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
570                 && defined(CONFIG_SPL_BUILD)) || \
571         ((defined(CONFIG_DRIVER_TI_CPSW) || \
572           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
573          !defined(CONFIG_SPL_BUILD))
574 int board_eth_init(bd_t *bis)
575 {
576         int rv, n = 0;
577         uint8_t mac_addr[6];
578         uint32_t mac_hi, mac_lo;
579         __maybe_unused struct am335x_baseboard_id header;
580
581         /* try reading mac address from efuse */
582         mac_lo = readl(&cdev->macid0l);
583         mac_hi = readl(&cdev->macid0h);
584         mac_addr[0] = mac_hi & 0xFF;
585         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
586         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
587         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
588         mac_addr[4] = mac_lo & 0xFF;
589         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
590
591 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
592         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
593         if (!getenv("ethaddr")) {
594                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
595
596                 if (is_valid_ethaddr(mac_addr))
597                         eth_setenv_enetaddr("ethaddr", mac_addr);
598         }
599
600 #ifdef CONFIG_DRIVER_TI_CPSW
601
602         mac_lo = readl(&cdev->macid1l);
603         mac_hi = readl(&cdev->macid1h);
604         mac_addr[0] = mac_hi & 0xFF;
605         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
606         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
607         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
608         mac_addr[4] = mac_lo & 0xFF;
609         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
610
611         if (!getenv("eth1addr")) {
612                 if (is_valid_ethaddr(mac_addr))
613                         eth_setenv_enetaddr("eth1addr", mac_addr);
614         }
615
616         if (read_eeprom(&header) < 0)
617                 puts("Could not get board ID.\n");
618
619         if (board_is_bone(&header) || board_is_bone_lt(&header) ||
620             board_is_idk(&header)) {
621                 writel(MII_MODE_ENABLE, &cdev->miisel);
622                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
623                                 PHY_INTERFACE_MODE_MII;
624         } else {
625                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
626                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
627                                 PHY_INTERFACE_MODE_RGMII;
628         }
629
630         rv = cpsw_register(&cpsw_data);
631         if (rv < 0)
632                 printf("Error %d registering CPSW switch\n", rv);
633         else
634                 n += rv;
635 #endif
636
637         /*
638          *
639          * CPSW RGMII Internal Delay Mode is not supported in all PVT
640          * operating points.  So we must set the TX clock delay feature
641          * in the AR8051 PHY.  Since we only support a single ethernet
642          * device in U-Boot, we only do this for the first instance.
643          */
644 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
645 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
646 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
647 #define AR8051_RGMII_TX_CLK_DLY         0x100
648
649         if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
650                 const char *devname;
651                 devname = miiphy_get_current_dev();
652
653                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
654                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
655                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
656                                 AR8051_RGMII_TX_CLK_DLY);
657         }
658 #endif
659 #if defined(CONFIG_USB_ETHER) && \
660         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
661         if (is_valid_ethaddr(mac_addr))
662                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
663
664         rv = usb_eth_initialize(bis);
665         if (rv < 0)
666                 printf("Error %d registering USB_ETHER\n", rv);
667         else
668                 n += rv;
669 #endif
670         return n;
671 }
672 #endif