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1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <errno.h>
13 #include <spl.h>
14 #include <serial.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/clk_synthesizer.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <asm/omap_sec_common.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <cpsw.h>
32 #include <power/tps65217.h>
33 #include <power/tps65910.h>
34 #include <environment.h>
35 #include <watchdog.h>
36 #include <environment.h>
37 #include "../common/board_detect.h"
38 #include "board.h"
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 /* GPIO that controls power to DDR on EVM-SK */
43 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
44 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
45 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
46 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
47 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
48 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
49 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
50 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
51 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
52
53 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54
55 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
56 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
57
58 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
59 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
60
61 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
62 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
63
64 /*
65  * Read header information from EEPROM into global structure.
66  */
67 #ifdef CONFIG_TI_I2C_BOARD_DETECT
68 void do_board_detect(void)
69 {
70         enable_i2c0_pin_mux();
71         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
72
73         if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
74                 printf("ti_i2c_eeprom_init failed\n");
75 }
76 #endif
77
78 #ifndef CONFIG_DM_SERIAL
79 struct serial_device *default_serial_console(void)
80 {
81         if (board_is_icev2())
82                 return &eserial4_device;
83         else
84                 return &eserial1_device;
85 }
86 #endif
87
88 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
89 static const struct ddr_data ddr2_data = {
90         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
91         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
92         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
93 };
94
95 static const struct cmd_control ddr2_cmd_ctrl_data = {
96         .cmd0csratio = MT47H128M16RT25E_RATIO,
97
98         .cmd1csratio = MT47H128M16RT25E_RATIO,
99
100         .cmd2csratio = MT47H128M16RT25E_RATIO,
101 };
102
103 static const struct emif_regs ddr2_emif_reg_data = {
104         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
105         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
106         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
107         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
108         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
109         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
110 };
111
112 static const struct ddr_data ddr3_data = {
113         .datardsratio0 = MT41J128MJT125_RD_DQS,
114         .datawdsratio0 = MT41J128MJT125_WR_DQS,
115         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
116         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
117 };
118
119 static const struct ddr_data ddr3_beagleblack_data = {
120         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
121         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
122         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
123         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
124 };
125
126 static const struct ddr_data ddr3_evm_data = {
127         .datardsratio0 = MT41J512M8RH125_RD_DQS,
128         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
129         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
130         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
131 };
132
133 static const struct ddr_data ddr3_icev2_data = {
134         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
135         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
136         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
137         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
138 };
139
140 static const struct cmd_control ddr3_cmd_ctrl_data = {
141         .cmd0csratio = MT41J128MJT125_RATIO,
142         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
143
144         .cmd1csratio = MT41J128MJT125_RATIO,
145         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
146
147         .cmd2csratio = MT41J128MJT125_RATIO,
148         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
149 };
150
151 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
152         .cmd0csratio = MT41K256M16HA125E_RATIO,
153         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
154
155         .cmd1csratio = MT41K256M16HA125E_RATIO,
156         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
157
158         .cmd2csratio = MT41K256M16HA125E_RATIO,
159         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
160 };
161
162 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
163         .cmd0csratio = MT41J512M8RH125_RATIO,
164         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
165
166         .cmd1csratio = MT41J512M8RH125_RATIO,
167         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
168
169         .cmd2csratio = MT41J512M8RH125_RATIO,
170         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
171 };
172
173 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
174         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
175         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
176
177         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
178         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
179
180         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
181         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
182 };
183
184 static struct emif_regs ddr3_emif_reg_data = {
185         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
186         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
187         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
188         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
189         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
190         .zq_config = MT41J128MJT125_ZQ_CFG,
191         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
192                                 PHY_EN_DYN_PWRDN,
193 };
194
195 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
196         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
197         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
198         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
199         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
200         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
201         .zq_config = MT41K256M16HA125E_ZQ_CFG,
202         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
203 };
204
205 static struct emif_regs ddr3_evm_emif_reg_data = {
206         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
207         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
208         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
209         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
210         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
211         .zq_config = MT41J512M8RH125_ZQ_CFG,
212         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
213                                 PHY_EN_DYN_PWRDN,
214 };
215
216 static struct emif_regs ddr3_icev2_emif_reg_data = {
217         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
218         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
219         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
220         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
221         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
222         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
223         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
224                                 PHY_EN_DYN_PWRDN,
225 };
226
227 #ifdef CONFIG_SPL_OS_BOOT
228 int spl_start_uboot(void)
229 {
230         /* break into full u-boot on 'c' */
231         if (serial_tstc() && serial_getc() == 'c')
232                 return 1;
233
234 #ifdef CONFIG_SPL_ENV_SUPPORT
235         env_init();
236         env_relocate_spec();
237         if (getenv_yesno("boot_os") != 1)
238                 return 1;
239 #endif
240
241         return 0;
242 }
243 #endif
244
245 #define OSC     (V_OSCK/1000000)
246 const struct dpll_params dpll_ddr = {
247                 266, OSC-1, 1, -1, -1, -1, -1};
248 const struct dpll_params dpll_ddr_evm_sk = {
249                 303, OSC-1, 1, -1, -1, -1, -1};
250 const struct dpll_params dpll_ddr_bone_black = {
251                 400, OSC-1, 1, -1, -1, -1, -1};
252
253 void am33xx_spl_board_init(void)
254 {
255         int mpu_vdd;
256
257         /* Get the frequency */
258         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
259
260         if (board_is_bone() || board_is_bone_lt()) {
261                 /* BeagleBone PMIC Code */
262                 int usb_cur_lim;
263
264                 /*
265                  * Only perform PMIC configurations if board rev > A1
266                  * on Beaglebone White
267                  */
268                 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
269                         return;
270
271                 if (i2c_probe(TPS65217_CHIP_PM))
272                         return;
273
274                 /*
275                  * On Beaglebone White we need to ensure we have AC power
276                  * before increasing the frequency.
277                  */
278                 if (board_is_bone()) {
279                         uchar pmic_status_reg;
280                         if (tps65217_reg_read(TPS65217_STATUS,
281                                               &pmic_status_reg))
282                                 return;
283                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
284                                 puts("No AC power, disabling frequency switch\n");
285                                 return;
286                         }
287                 }
288
289                 /*
290                  * Override what we have detected since we know if we have
291                  * a Beaglebone Black it supports 1GHz.
292                  */
293                 if (board_is_bone_lt())
294                         dpll_mpu_opp100.m = MPUPLL_M_1000;
295
296                 /*
297                  * Increase USB current limit to 1300mA or 1800mA and set
298                  * the MPU voltage controller as needed.
299                  */
300                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
301                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
302                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
303                 } else {
304                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
305                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
306                 }
307
308                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
309                                        TPS65217_POWER_PATH,
310                                        usb_cur_lim,
311                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
312                         puts("tps65217_reg_write failure\n");
313
314                 /* Set DCDC3 (CORE) voltage to 1.125V */
315                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
316                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
317                         puts("tps65217_voltage_update failure\n");
318                         return;
319                 }
320
321                 /* Set CORE Frequencies to OPP100 */
322                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
323
324                 /* Set DCDC2 (MPU) voltage */
325                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
326                         puts("tps65217_voltage_update failure\n");
327                         return;
328                 }
329
330                 /*
331                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
332                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
333                  */
334                 if (board_is_bone()) {
335                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
336                                                TPS65217_DEFLS1,
337                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
338                                                TPS65217_LDO_MASK))
339                                 puts("tps65217_reg_write failure\n");
340                 } else {
341                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
342                                                TPS65217_DEFLS1,
343                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
344                                                TPS65217_LDO_MASK))
345                                 puts("tps65217_reg_write failure\n");
346                 }
347
348                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
349                                        TPS65217_DEFLS2,
350                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
351                                        TPS65217_LDO_MASK))
352                         puts("tps65217_reg_write failure\n");
353         } else {
354                 int sil_rev;
355
356                 /*
357                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
358                  * MPU frequencies we support we use a CORE voltage of
359                  * 1.1375V.  For MPU voltage we need to switch based on
360                  * the frequency we are running at.
361                  */
362                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
363                         return;
364
365                 /*
366                  * Depending on MPU clock and PG we will need a different
367                  * VDD to drive at that speed.
368                  */
369                 sil_rev = readl(&cdev->deviceid) >> 28;
370                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
371                                                       dpll_mpu_opp100.m);
372
373                 /* Tell the TPS65910 to use i2c */
374                 tps65910_set_i2c_control();
375
376                 /* First update MPU voltage. */
377                 if (tps65910_voltage_update(MPU, mpu_vdd))
378                         return;
379
380                 /* Second, update the CORE voltage. */
381                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
382                         return;
383
384                 /* Set CORE Frequencies to OPP100 */
385                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
386         }
387
388         /* Set MPU Frequency to what we detected now that voltages are set */
389         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
390 }
391
392 const struct dpll_params *get_dpll_ddr_params(void)
393 {
394         if (board_is_evm_sk())
395                 return &dpll_ddr_evm_sk;
396         else if (board_is_bone_lt() || board_is_icev2())
397                 return &dpll_ddr_bone_black;
398         else if (board_is_evm_15_or_later())
399                 return &dpll_ddr_evm_sk;
400         else
401                 return &dpll_ddr;
402 }
403
404 void set_uart_mux_conf(void)
405 {
406 #if CONFIG_CONS_INDEX == 1
407         enable_uart0_pin_mux();
408 #elif CONFIG_CONS_INDEX == 2
409         enable_uart1_pin_mux();
410 #elif CONFIG_CONS_INDEX == 3
411         enable_uart2_pin_mux();
412 #elif CONFIG_CONS_INDEX == 4
413         enable_uart3_pin_mux();
414 #elif CONFIG_CONS_INDEX == 5
415         enable_uart4_pin_mux();
416 #elif CONFIG_CONS_INDEX == 6
417         enable_uart5_pin_mux();
418 #endif
419 }
420
421 void set_mux_conf_regs(void)
422 {
423         enable_board_pin_mux();
424 }
425
426 const struct ctrl_ioregs ioregs_evmsk = {
427         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
428         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
429         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
430         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
431         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
432 };
433
434 const struct ctrl_ioregs ioregs_bonelt = {
435         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
436         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
437         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
438         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
439         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
440 };
441
442 const struct ctrl_ioregs ioregs_evm15 = {
443         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
444         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
445         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
446         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
447         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
448 };
449
450 const struct ctrl_ioregs ioregs = {
451         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
452         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
453         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
454         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
455         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
456 };
457
458 void sdram_init(void)
459 {
460         if (board_is_evm_sk()) {
461                 /*
462                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
463                  * This is safe enough to do on older revs.
464                  */
465                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
466                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
467         }
468
469         if (board_is_icev2()) {
470                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
471                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
472         }
473
474         if (board_is_evm_sk())
475                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
476                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
477         else if (board_is_bone_lt())
478                 config_ddr(400, &ioregs_bonelt,
479                            &ddr3_beagleblack_data,
480                            &ddr3_beagleblack_cmd_ctrl_data,
481                            &ddr3_beagleblack_emif_reg_data, 0);
482         else if (board_is_evm_15_or_later())
483                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
484                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
485         else if (board_is_icev2())
486                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
487                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
488                            0);
489         else
490                 config_ddr(266, &ioregs, &ddr2_data,
491                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
492 }
493 #endif
494
495 #if !defined(CONFIG_SPL_BUILD) || \
496         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
497 static void request_and_set_gpio(int gpio, char *name, int val)
498 {
499         int ret;
500
501         ret = gpio_request(gpio, name);
502         if (ret < 0) {
503                 printf("%s: Unable to request %s\n", __func__, name);
504                 return;
505         }
506
507         ret = gpio_direction_output(gpio, 0);
508         if (ret < 0) {
509                 printf("%s: Unable to set %s  as output\n", __func__, name);
510                 goto err_free_gpio;
511         }
512
513         gpio_set_value(gpio, val);
514
515         return;
516
517 err_free_gpio:
518         gpio_free(gpio);
519 }
520
521 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
522 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
523
524 /**
525  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
526  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
527  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
528  * give 50MHz output for Eth0 and 1.
529  */
530 static struct clk_synth cdce913_data = {
531         .id = 0x81,
532         .capacitor = 0x90,
533         .mux = 0x6d,
534         .pdiv2 = 0x2,
535         .pdiv3 = 0x2,
536 };
537 #endif
538
539 /*
540  * Basic board specific setup.  Pinmux has been handled already.
541  */
542 int board_init(void)
543 {
544 #if defined(CONFIG_HW_WATCHDOG)
545         hw_watchdog_init();
546 #endif
547
548         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
549 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
550         gpmc_init();
551 #endif
552
553 #if !defined(CONFIG_SPL_BUILD) || \
554         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
555         if (board_is_icev2()) {
556                 int rv;
557                 u32 reg;
558
559                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
560                 /* Make J19 status available on GPIO1_26 */
561                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
562
563                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
564                 /*
565                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
566                  * jumpers near the port. Read the jumper value and set
567                  * the pinmux, external mux and PHY clock accordingly.
568                  * As jumper line is overridden by PHY RX_DV pin immediately
569                  * after bootstrap (power-up/reset), we need to sample
570                  * it during PHY reset using GPIO rising edge detection.
571                  */
572                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
573                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
574                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
575                 writel(reg, GPIO0_RISINGDETECT);
576                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
577                 writel(reg, GPIO1_RISINGDETECT);
578                 /* Reset PHYs to capture the Jumper setting */
579                 gpio_set_value(GPIO_PHY_RESET, 0);
580                 udelay(2);      /* PHY datasheet states 1uS min. */
581                 gpio_set_value(GPIO_PHY_RESET, 1);
582
583                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
584                 if (reg) {
585                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
586                         /* RMII mode */
587                         printf("ETH0, CPSW\n");
588                 } else {
589                         /* MII mode */
590                         printf("ETH0, PRU\n");
591                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
592                 }
593
594                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
595                 if (reg) {
596                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
597                         /* RMII mode */
598                         printf("ETH1, CPSW\n");
599                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
600                 } else {
601                         /* MII mode */
602                         printf("ETH1, PRU\n");
603                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
604                 }
605
606                 /* disable rising edge IRQs */
607                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
608                 writel(reg, GPIO0_RISINGDETECT);
609                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
610                 writel(reg, GPIO1_RISINGDETECT);
611
612                 rv = setup_clock_synthesizer(&cdce913_data);
613                 if (rv) {
614                         printf("Clock synthesizer setup failed %d\n", rv);
615                         return rv;
616                 }
617
618                 /* reset PHYs */
619                 gpio_set_value(GPIO_PHY_RESET, 0);
620                 udelay(2);      /* PHY datasheet states 1uS min. */
621                 gpio_set_value(GPIO_PHY_RESET, 1);
622         }
623 #endif
624
625         return 0;
626 }
627
628 #ifdef CONFIG_BOARD_LATE_INIT
629 int board_late_init(void)
630 {
631 #if !defined(CONFIG_SPL_BUILD)
632         uint8_t mac_addr[6];
633         uint32_t mac_hi, mac_lo;
634 #endif
635
636 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
637         char *name = NULL;
638
639         if (board_is_bbg1())
640                 name = "BBG1";
641         set_board_info_env(name);
642 #endif
643
644 #if !defined(CONFIG_SPL_BUILD)
645         /* try reading mac address from efuse */
646         mac_lo = readl(&cdev->macid0l);
647         mac_hi = readl(&cdev->macid0h);
648         mac_addr[0] = mac_hi & 0xFF;
649         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
650         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
651         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
652         mac_addr[4] = mac_lo & 0xFF;
653         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
654
655         if (!getenv("ethaddr")) {
656                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
657
658                 if (is_valid_ethaddr(mac_addr))
659                         eth_setenv_enetaddr("ethaddr", mac_addr);
660         }
661
662         mac_lo = readl(&cdev->macid1l);
663         mac_hi = readl(&cdev->macid1h);
664         mac_addr[0] = mac_hi & 0xFF;
665         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
666         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
667         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
668         mac_addr[4] = mac_lo & 0xFF;
669         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
670
671         if (!getenv("eth1addr")) {
672                 if (is_valid_ethaddr(mac_addr))
673                         eth_setenv_enetaddr("eth1addr", mac_addr);
674         }
675 #endif
676
677         return 0;
678 }
679 #endif
680
681 #ifndef CONFIG_DM_ETH
682
683 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
684         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
685 static void cpsw_control(int enabled)
686 {
687         /* VTP can be added here */
688
689         return;
690 }
691
692 static struct cpsw_slave_data cpsw_slaves[] = {
693         {
694                 .slave_reg_ofs  = 0x208,
695                 .sliver_reg_ofs = 0xd80,
696                 .phy_addr       = 0,
697         },
698         {
699                 .slave_reg_ofs  = 0x308,
700                 .sliver_reg_ofs = 0xdc0,
701                 .phy_addr       = 1,
702         },
703 };
704
705 static struct cpsw_platform_data cpsw_data = {
706         .mdio_base              = CPSW_MDIO_BASE,
707         .cpsw_base              = CPSW_BASE,
708         .mdio_div               = 0xff,
709         .channels               = 8,
710         .cpdma_reg_ofs          = 0x800,
711         .slaves                 = 1,
712         .slave_data             = cpsw_slaves,
713         .ale_reg_ofs            = 0xd00,
714         .ale_entries            = 1024,
715         .host_port_reg_ofs      = 0x108,
716         .hw_stats_reg_ofs       = 0x900,
717         .bd_ram_ofs             = 0x2000,
718         .mac_control            = (1 << 5),
719         .control                = cpsw_control,
720         .host_port_num          = 0,
721         .version                = CPSW_CTRL_VERSION_2,
722 };
723 #endif
724
725 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
726         defined(CONFIG_SPL_BUILD)) || \
727         ((defined(CONFIG_DRIVER_TI_CPSW) || \
728           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
729          !defined(CONFIG_SPL_BUILD))
730
731 /*
732  * This function will:
733  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
734  * in the environment
735  * Perform fixups to the PHY present on certain boards.  We only need this
736  * function in:
737  * - SPL with either CPSW or USB ethernet support
738  * - Full U-Boot, with either CPSW or USB ethernet
739  * Build in only these cases to avoid warnings about unused variables
740  * when we build an SPL that has neither option but full U-Boot will.
741  */
742 int board_eth_init(bd_t *bis)
743 {
744         int rv, n = 0;
745 #if defined(CONFIG_USB_ETHER) && \
746         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
747         uint8_t mac_addr[6];
748         uint32_t mac_hi, mac_lo;
749
750         /*
751          * use efuse mac address for USB ethernet as we know that
752          * both CPSW and USB ethernet will never be active at the same time
753          */
754         mac_lo = readl(&cdev->macid0l);
755         mac_hi = readl(&cdev->macid0h);
756         mac_addr[0] = mac_hi & 0xFF;
757         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
758         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
759         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
760         mac_addr[4] = mac_lo & 0xFF;
761         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
762 #endif
763
764
765 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
766         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
767
768 #ifdef CONFIG_DRIVER_TI_CPSW
769         if (board_is_bone() || board_is_bone_lt() ||
770             board_is_idk()) {
771                 writel(MII_MODE_ENABLE, &cdev->miisel);
772                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
773                                 PHY_INTERFACE_MODE_MII;
774         } else if (board_is_icev2()) {
775                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
776                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
777                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
778                 cpsw_slaves[0].phy_addr = 1;
779                 cpsw_slaves[1].phy_addr = 3;
780         } else {
781                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
782                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
783                                 PHY_INTERFACE_MODE_RGMII;
784         }
785
786         rv = cpsw_register(&cpsw_data);
787         if (rv < 0)
788                 printf("Error %d registering CPSW switch\n", rv);
789         else
790                 n += rv;
791 #endif
792
793         /*
794          *
795          * CPSW RGMII Internal Delay Mode is not supported in all PVT
796          * operating points.  So we must set the TX clock delay feature
797          * in the AR8051 PHY.  Since we only support a single ethernet
798          * device in U-Boot, we only do this for the first instance.
799          */
800 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
801 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
802 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
803 #define AR8051_RGMII_TX_CLK_DLY         0x100
804
805         if (board_is_evm_sk() || board_is_gp_evm()) {
806                 const char *devname;
807                 devname = miiphy_get_current_dev();
808
809                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
810                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
811                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
812                                 AR8051_RGMII_TX_CLK_DLY);
813         }
814 #endif
815 #if defined(CONFIG_USB_ETHER) && \
816         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
817         if (is_valid_ethaddr(mac_addr))
818                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
819
820         rv = usb_eth_initialize(bis);
821         if (rv < 0)
822                 printf("Error %d registering USB_ETHER\n", rv);
823         else
824                 n += rv;
825 #endif
826         return n;
827 }
828 #endif
829
830 #endif /* CONFIG_DM_ETH */
831
832 #ifdef CONFIG_SPL_LOAD_FIT
833 int board_fit_config_name_match(const char *name)
834 {
835         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
836                 return 0;
837         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
838                 return 0;
839         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
840                 return 0;
841         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
842                 return 0;
843         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
844                 return 0;
845         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
846                 return 0;
847         else
848                 return -1;
849 }
850 #endif
851
852 #ifdef CONFIG_TI_SECURE_DEVICE
853 void board_fit_image_post_process(void **p_image, size_t *p_size)
854 {
855         secure_boot_verify_image(p_image, p_size);
856 }
857 #endif