git.sur5r.net Git - u-boot/blob - board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <serial.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/clk_synthesizer.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mem.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27 #include <asm/gpio.h>
  28 #include <asm/omap_sec_common.h>
  29 #include <i2c.h>
  30 #include <miiphy.h>
  31 #include <cpsw.h>
  32 #include <power/tps65217.h>
  33 #include <power/tps65910.h>
  34 #include <environment.h>
  35 #include <watchdog.h>
  36 #include <environment.h>
  37 #include "../common/board_detect.h"
  38 #include "board.h"
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* GPIO that controls power to DDR on EVM-SK */
  43 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  44 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  45 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  46 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  47 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  48 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  49 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  50 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  51 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  52
  53 #if defined(CONFIG_SPL_BUILD) || \
  54         (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
  55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  56 #endif
  57
  58 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  59 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  60
  61 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  62 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  63
  64 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  65 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  66
  67 /*
  68  * Read header information from EEPROM into global structure.
  69  */
  70 static inline int __maybe_unused read_eeprom(void)
  71 {
  72         return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
  73 }
  74
  75 #ifndef CONFIG_DM_SERIAL
  76 struct serial_device *default_serial_console(void)
  77 {
  78         if (board_is_icev2())
  79                 return &eserial4_device;
  80         else
  81                 return &eserial1_device;
  82 }
  83 #endif
  84
  85 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  86 static const struct ddr_data ddr2_data = {
  87         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  88         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  89         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  90 };
  91
  92 static const struct cmd_control ddr2_cmd_ctrl_data = {
  93         .cmd0csratio = MT47H128M16RT25E_RATIO,
  94
  95         .cmd1csratio = MT47H128M16RT25E_RATIO,
  96
  97         .cmd2csratio = MT47H128M16RT25E_RATIO,
  98 };
  99
 100 static const struct emif_regs ddr2_emif_reg_data = {
 101         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 102         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 103         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 104         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 105         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 106         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 107 };
 108
 109 static const struct ddr_data ddr3_data = {
 110         .datardsratio0 = MT41J128MJT125_RD_DQS,
 111         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 112         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 113         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 114 };
 115
 116 static const struct ddr_data ddr3_beagleblack_data = {
 117         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 118         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 119         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 120         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 121 };
 122
 123 static const struct ddr_data ddr3_evm_data = {
 124         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 125         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 126         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 127         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 128 };
 129
 130 static const struct ddr_data ddr3_icev2_data = {
 131         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 132         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 133         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 134         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 135 };
 136
 137 static const struct cmd_control ddr3_cmd_ctrl_data = {
 138         .cmd0csratio = MT41J128MJT125_RATIO,
 139         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 140
 141         .cmd1csratio = MT41J128MJT125_RATIO,
 142         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 143
 144         .cmd2csratio = MT41J128MJT125_RATIO,
 145         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 146 };
 147
 148 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 149         .cmd0csratio = MT41K256M16HA125E_RATIO,
 150         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 151
 152         .cmd1csratio = MT41K256M16HA125E_RATIO,
 153         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 154
 155         .cmd2csratio = MT41K256M16HA125E_RATIO,
 156         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 157 };
 158
 159 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 160         .cmd0csratio = MT41J512M8RH125_RATIO,
 161         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 162
 163         .cmd1csratio = MT41J512M8RH125_RATIO,
 164         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 165
 166         .cmd2csratio = MT41J512M8RH125_RATIO,
 167         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 168 };
 169
 170 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 171         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 172         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 173
 174         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 175         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 176
 177         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 178         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 179 };
 180
 181 static struct emif_regs ddr3_emif_reg_data = {
 182         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 183         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 184         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 185         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 186         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 187         .zq_config = MT41J128MJT125_ZQ_CFG,
 188         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 189                                 PHY_EN_DYN_PWRDN,
 190 };
 191
 192 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 193         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 194         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 195         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 196         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 197         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 198         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 199         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 200 };
 201
 202 static struct emif_regs ddr3_evm_emif_reg_data = {
 203         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 204         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 205         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 206         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 207         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 208         .zq_config = MT41J512M8RH125_ZQ_CFG,
 209         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 210                                 PHY_EN_DYN_PWRDN,
 211 };
 212
 213 static struct emif_regs ddr3_icev2_emif_reg_data = {
 214         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 215         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 216         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 217         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 218         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 219         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 220         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 221                                 PHY_EN_DYN_PWRDN,
 222 };
 223
 224 #ifdef CONFIG_SPL_OS_BOOT
 225 int spl_start_uboot(void)
 226 {
 227         /* break into full u-boot on 'c' */
 228         if (serial_tstc() && serial_getc() == 'c')
 229                 return 1;
 230
 231 #ifdef CONFIG_SPL_ENV_SUPPORT
 232         env_init();
 233         env_relocate_spec();
 234         if (getenv_yesno("boot_os") != 1)
 235                 return 1;
 236 #endif
 237
 238         return 0;
 239 }
 240 #endif
 241
 242 #define OSC     (V_OSCK/1000000)
 243 const struct dpll_params dpll_ddr = {
 244                 266, OSC-1, 1, -1, -1, -1, -1};
 245 const struct dpll_params dpll_ddr_evm_sk = {
 246                 303, OSC-1, 1, -1, -1, -1, -1};
 247 const struct dpll_params dpll_ddr_bone_black = {
 248                 400, OSC-1, 1, -1, -1, -1, -1};
 249
 250 void am33xx_spl_board_init(void)
 251 {
 252         int mpu_vdd;
 253
 254         if (read_eeprom() < 0)
 255                 puts("Could not get board ID.\n");
 256
 257         /* Get the frequency */
 258         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 259
 260         if (board_is_bone() || board_is_bone_lt()) {
 261                 /* BeagleBone PMIC Code */
 262                 int usb_cur_lim;
 263
 264                 /*
 265                  * Only perform PMIC configurations if board rev > A1
 266                  * on Beaglebone White
 267                  */
 268                 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 269                         return;
 270
 271                 if (i2c_probe(TPS65217_CHIP_PM))
 272                         return;
 273
 274                 /*
 275                  * On Beaglebone White we need to ensure we have AC power
 276                  * before increasing the frequency.
 277                  */
 278                 if (board_is_bone()) {
 279                         uchar pmic_status_reg;
 280                         if (tps65217_reg_read(TPS65217_STATUS,
 281                                               &pmic_status_reg))
 282                                 return;
 283                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 284                                 puts("No AC power, disabling frequency switch\n");
 285                                 return;
 286                         }
 287                 }
 288
 289                 /*
 290                  * Override what we have detected since we know if we have
 291                  * a Beaglebone Black it supports 1GHz.
 292                  */
 293                 if (board_is_bone_lt())
 294                         dpll_mpu_opp100.m = MPUPLL_M_1000;
 295
 296                 /*
 297                  * Increase USB current limit to 1300mA or 1800mA and set
 298                  * the MPU voltage controller as needed.
 299                  */
 300                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 301                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 302                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 303                 } else {
 304                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 305                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 306                 }
 307
 308                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 309                                        TPS65217_POWER_PATH,
 310                                        usb_cur_lim,
 311                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 312                         puts("tps65217_reg_write failure\n");
 313
 314                 /* Set DCDC3 (CORE) voltage to 1.125V */
 315                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 316                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
 317                         puts("tps65217_voltage_update failure\n");
 318                         return;
 319                 }
 320
 321                 /* Set CORE Frequencies to OPP100 */
 322                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 323
 324                 /* Set DCDC2 (MPU) voltage */
 325                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 326                         puts("tps65217_voltage_update failure\n");
 327                         return;
 328                 }
 329
 330                 /*
 331                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 332                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 333                  */
 334                 if (board_is_bone()) {
 335                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 336                                                TPS65217_DEFLS1,
 337                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 338                                                TPS65217_LDO_MASK))
 339                                 puts("tps65217_reg_write failure\n");
 340                 } else {
 341                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 342                                                TPS65217_DEFLS1,
 343                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 344                                                TPS65217_LDO_MASK))
 345                                 puts("tps65217_reg_write failure\n");
 346                 }
 347
 348                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 349                                        TPS65217_DEFLS2,
 350                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 351                                        TPS65217_LDO_MASK))
 352                         puts("tps65217_reg_write failure\n");
 353         } else {
 354                 int sil_rev;
 355
 356                 /*
 357                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 358                  * MPU frequencies we support we use a CORE voltage of
 359                  * 1.1375V.  For MPU voltage we need to switch based on
 360                  * the frequency we are running at.
 361                  */
 362                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 363                         return;
 364
 365                 /*
 366                  * Depending on MPU clock and PG we will need a different
 367                  * VDD to drive at that speed.
 368                  */
 369                 sil_rev = readl(&cdev->deviceid) >> 28;
 370                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 371                                                       dpll_mpu_opp100.m);
 372
 373                 /* Tell the TPS65910 to use i2c */
 374                 tps65910_set_i2c_control();
 375
 376                 /* First update MPU voltage. */
 377                 if (tps65910_voltage_update(MPU, mpu_vdd))
 378                         return;
 379
 380                 /* Second, update the CORE voltage. */
 381                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 382                         return;
 383
 384                 /* Set CORE Frequencies to OPP100 */
 385                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 386         }
 387
 388         /* Set MPU Frequency to what we detected now that voltages are set */
 389         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 390 }
 391
 392 const struct dpll_params *get_dpll_ddr_params(void)
 393 {
 394         enable_i2c0_pin_mux();
 395         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 396         if (read_eeprom() < 0)
 397                 puts("Could not get board ID.\n");
 398
 399         if (board_is_evm_sk())
 400                 return &dpll_ddr_evm_sk;
 401         else if (board_is_bone_lt() || board_is_icev2())
 402                 return &dpll_ddr_bone_black;
 403         else if (board_is_evm_15_or_later())
 404                 return &dpll_ddr_evm_sk;
 405         else
 406                 return &dpll_ddr;
 407 }
 408
 409 void set_uart_mux_conf(void)
 410 {
 411 #if CONFIG_CONS_INDEX == 1
 412         enable_uart0_pin_mux();
 413 #elif CONFIG_CONS_INDEX == 2
 414         enable_uart1_pin_mux();
 415 #elif CONFIG_CONS_INDEX == 3
 416         enable_uart2_pin_mux();
 417 #elif CONFIG_CONS_INDEX == 4
 418         enable_uart3_pin_mux();
 419 #elif CONFIG_CONS_INDEX == 5
 420         enable_uart4_pin_mux();
 421 #elif CONFIG_CONS_INDEX == 6
 422         enable_uart5_pin_mux();
 423 #endif
 424 }
 425
 426 void set_mux_conf_regs(void)
 427 {
 428         if (read_eeprom() < 0)
 429                 puts("Could not get board ID.\n");
 430
 431         enable_board_pin_mux();
 432 }
 433
 434 const struct ctrl_ioregs ioregs_evmsk = {
 435         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 436         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 437         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 438         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 439         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 440 };
 441
 442 const struct ctrl_ioregs ioregs_bonelt = {
 443         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 444         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 445         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 446         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 447         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 448 };
 449
 450 const struct ctrl_ioregs ioregs_evm15 = {
 451         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 452         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 453         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 454         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 455         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 456 };
 457
 458 const struct ctrl_ioregs ioregs = {
 459         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 460         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 461         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 462         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 463         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 464 };
 465
 466 void sdram_init(void)
 467 {
 468         if (read_eeprom() < 0)
 469                 puts("Could not get board ID.\n");
 470
 471         if (board_is_evm_sk()) {
 472                 /*
 473                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 474                  * This is safe enough to do on older revs.
 475                  */
 476                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 477                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 478         }
 479
 480         if (board_is_icev2()) {
 481                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 482                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 483         }
 484
 485         if (board_is_evm_sk())
 486                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 487                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 488         else if (board_is_bone_lt())
 489                 config_ddr(400, &ioregs_bonelt,
 490                            &ddr3_beagleblack_data,
 491                            &ddr3_beagleblack_cmd_ctrl_data,
 492                            &ddr3_beagleblack_emif_reg_data, 0);
 493         else if (board_is_evm_15_or_later())
 494                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 495                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 496         else if (board_is_icev2())
 497                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 498                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 499                            0);
 500         else
 501                 config_ddr(266, &ioregs, &ddr2_data,
 502                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 503 }
 504 #endif
 505
 506 #if !defined(CONFIG_SPL_BUILD) || \
 507         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 508 static void request_and_set_gpio(int gpio, char *name, int val)
 509 {
 510         int ret;
 511
 512         ret = gpio_request(gpio, name);
 513         if (ret < 0) {
 514                 printf("%s: Unable to request %s\n", __func__, name);
 515                 return;
 516         }
 517
 518         ret = gpio_direction_output(gpio, 0);
 519         if (ret < 0) {
 520                 printf("%s: Unable to set %s  as output\n", __func__, name);
 521                 goto err_free_gpio;
 522         }
 523
 524         gpio_set_value(gpio, val);
 525
 526         return;
 527
 528 err_free_gpio:
 529         gpio_free(gpio);
 530 }
 531
 532 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 533 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 534
 535 /**
 536  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 537  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 538  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 539  * give 50MHz output for Eth0 and 1.
 540  */
 541 static struct clk_synth cdce913_data = {
 542         .id = 0x81,
 543         .capacitor = 0x90,
 544         .mux = 0x6d,
 545         .pdiv2 = 0x2,
 546         .pdiv3 = 0x2,
 547 };
 548 #endif
 549
 550 /*
 551  * Basic board specific setup.  Pinmux has been handled already.
 552  */
 553 int board_init(void)
 554 {
 555 #if defined(CONFIG_HW_WATCHDOG)
 556         hw_watchdog_init();
 557 #endif
 558
 559         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 560 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 561         gpmc_init();
 562 #endif
 563
 564 #if !defined(CONFIG_SPL_BUILD) || \
 565         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 566         if (board_is_icev2()) {
 567                 int rv;
 568                 u32 reg;
 569
 570                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 571                 /* Make J19 status available on GPIO1_26 */
 572                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 573
 574                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 575                 /*
 576                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 577                  * jumpers near the port. Read the jumper value and set
 578                  * the pinmux, external mux and PHY clock accordingly.
 579                  * As jumper line is overridden by PHY RX_DV pin immediately
 580                  * after bootstrap (power-up/reset), we need to sample
 581                  * it during PHY reset using GPIO rising edge detection.
 582                  */
 583                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 584                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 585                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 586                 writel(reg, GPIO0_RISINGDETECT);
 587                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 588                 writel(reg, GPIO1_RISINGDETECT);
 589                 /* Reset PHYs to capture the Jumper setting */
 590                 gpio_set_value(GPIO_PHY_RESET, 0);
 591                 udelay(2);      /* PHY datasheet states 1uS min. */
 592                 gpio_set_value(GPIO_PHY_RESET, 1);
 593
 594                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 595                 if (reg) {
 596                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 597                         /* RMII mode */
 598                         printf("ETH0, CPSW\n");
 599                 } else {
 600                         /* MII mode */
 601                         printf("ETH0, PRU\n");
 602                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 603                 }
 604
 605                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 606                 if (reg) {
 607                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 608                         /* RMII mode */
 609                         printf("ETH1, CPSW\n");
 610                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 611                 } else {
 612                         /* MII mode */
 613                         printf("ETH1, PRU\n");
 614                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 615                 }
 616
 617                 /* disable rising edge IRQs */
 618                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 619                 writel(reg, GPIO0_RISINGDETECT);
 620                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 621                 writel(reg, GPIO1_RISINGDETECT);
 622
 623                 rv = setup_clock_synthesizer(&cdce913_data);
 624                 if (rv) {
 625                         printf("Clock synthesizer setup failed %d\n", rv);
 626                         return rv;
 627                 }
 628
 629                 /* reset PHYs */
 630                 gpio_set_value(GPIO_PHY_RESET, 0);
 631                 udelay(2);      /* PHY datasheet states 1uS min. */
 632                 gpio_set_value(GPIO_PHY_RESET, 1);
 633         }
 634 #endif
 635
 636         return 0;
 637 }
 638
 639 #ifdef CONFIG_BOARD_LATE_INIT
 640 int board_late_init(void)
 641 {
 642 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 643         int rc;
 644         char *name = NULL;
 645
 646         rc = read_eeprom();
 647         if (rc)
 648                 puts("Could not get board ID.\n");
 649
 650         if (board_is_bbg1())
 651                 name = "BBG1";
 652         set_board_info_env(name);
 653 #endif
 654
 655         return 0;
 656 }
 657 #endif
 658
 659 #ifndef CONFIG_DM_ETH
 660
 661 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 662         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 663 static void cpsw_control(int enabled)
 664 {
 665         /* VTP can be added here */
 666
 667         return;
 668 }
 669
 670 static struct cpsw_slave_data cpsw_slaves[] = {
 671         {
 672                 .slave_reg_ofs  = 0x208,
 673                 .sliver_reg_ofs = 0xd80,
 674                 .phy_addr       = 0,
 675         },
 676         {
 677                 .slave_reg_ofs  = 0x308,
 678                 .sliver_reg_ofs = 0xdc0,
 679                 .phy_addr       = 1,
 680         },
 681 };
 682
 683 static struct cpsw_platform_data cpsw_data = {
 684         .mdio_base              = CPSW_MDIO_BASE,
 685         .cpsw_base              = CPSW_BASE,
 686         .mdio_div               = 0xff,
 687         .channels               = 8,
 688         .cpdma_reg_ofs          = 0x800,
 689         .slaves                 = 1,
 690         .slave_data             = cpsw_slaves,
 691         .ale_reg_ofs            = 0xd00,
 692         .ale_entries            = 1024,
 693         .host_port_reg_ofs      = 0x108,
 694         .hw_stats_reg_ofs       = 0x900,
 695         .bd_ram_ofs             = 0x2000,
 696         .mac_control            = (1 << 5),
 697         .control                = cpsw_control,
 698         .host_port_num          = 0,
 699         .version                = CPSW_CTRL_VERSION_2,
 700 };
 701 #endif
 702
 703 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
 704         defined(CONFIG_SPL_BUILD)) || \
 705         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 706           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 707          !defined(CONFIG_SPL_BUILD))
 708
 709 /*
 710  * This function will:
 711  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 712  * in the environment
 713  * Perform fixups to the PHY present on certain boards.  We only need this
 714  * function in:
 715  * - SPL with either CPSW or USB ethernet support
 716  * - Full U-Boot, with either CPSW or USB ethernet
 717  * Build in only these cases to avoid warnings about unused variables
 718  * when we build an SPL that has neither option but full U-Boot will.
 719  */
 720 int board_eth_init(bd_t *bis)
 721 {
 722         int rv, n = 0;
 723         uint8_t mac_addr[6];
 724         uint32_t mac_hi, mac_lo;
 725         __maybe_unused struct ti_am_eeprom *header;
 726
 727         /* try reading mac address from efuse */
 728         mac_lo = readl(&cdev->macid0l);
 729         mac_hi = readl(&cdev->macid0h);
 730         mac_addr[0] = mac_hi & 0xFF;
 731         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 732         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 733         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 734         mac_addr[4] = mac_lo & 0xFF;
 735         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 736
 737 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 738         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 739         if (!getenv("ethaddr")) {
 740                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 741
 742                 if (is_valid_ethaddr(mac_addr))
 743                         eth_setenv_enetaddr("ethaddr", mac_addr);
 744         }
 745
 746 #ifdef CONFIG_DRIVER_TI_CPSW
 747
 748         mac_lo = readl(&cdev->macid1l);
 749         mac_hi = readl(&cdev->macid1h);
 750         mac_addr[0] = mac_hi & 0xFF;
 751         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 752         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 753         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 754         mac_addr[4] = mac_lo & 0xFF;
 755         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 756
 757         if (!getenv("eth1addr")) {
 758                 if (is_valid_ethaddr(mac_addr))
 759                         eth_setenv_enetaddr("eth1addr", mac_addr);
 760         }
 761
 762         if (read_eeprom() < 0)
 763                 puts("Could not get board ID.\n");
 764
 765         if (board_is_bone() || board_is_bone_lt() ||
 766             board_is_idk()) {
 767                 writel(MII_MODE_ENABLE, &cdev->miisel);
 768                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 769                                 PHY_INTERFACE_MODE_MII;
 770         } else if (board_is_icev2()) {
 771                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 772                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 773                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
 774                 cpsw_slaves[0].phy_addr = 1;
 775                 cpsw_slaves[1].phy_addr = 3;
 776         } else {
 777                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 778                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 779                                 PHY_INTERFACE_MODE_RGMII;
 780         }
 781
 782         rv = cpsw_register(&cpsw_data);
 783         if (rv < 0)
 784                 printf("Error %d registering CPSW switch\n", rv);
 785         else
 786                 n += rv;
 787 #endif
 788
 789         /*
 790          *
 791          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 792          * operating points.  So we must set the TX clock delay feature
 793          * in the AR8051 PHY.  Since we only support a single ethernet
 794          * device in U-Boot, we only do this for the first instance.
 795          */
 796 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 797 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 798 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 799 #define AR8051_RGMII_TX_CLK_DLY         0x100
 800
 801         if (board_is_evm_sk() || board_is_gp_evm()) {
 802                 const char *devname;
 803                 devname = miiphy_get_current_dev();
 804
 805                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 806                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 807                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 808                                 AR8051_RGMII_TX_CLK_DLY);
 809         }
 810 #endif
 811 #if defined(CONFIG_USB_ETHER) && \
 812         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 813         if (is_valid_ethaddr(mac_addr))
 814                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 815
 816         rv = usb_eth_initialize(bis);
 817         if (rv < 0)
 818                 printf("Error %d registering USB_ETHER\n", rv);
 819         else
 820                 n += rv;
 821 #endif
 822         return n;
 823 }
 824 #endif
 825
 826 #endif /* CONFIG_DM_ETH */
 827
 828 #ifdef CONFIG_SPL_LOAD_FIT
 829 int board_fit_config_name_match(const char *name)
 830 {
 831         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 832                 return 0;
 833         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 834                 return 0;
 835         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 836                 return 0;
 837         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 838                 return 0;
 839         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 840                 return 0;
 841         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 842                 return 0;
 843         else
 844                 return -1;
 845 }
 846 #endif
 847
 848 #ifdef CONFIG_TI_SECURE_DEVICE
 849 void board_fit_image_post_process(void **p_image, size_t *p_size)
 850 {
 851         secure_boot_verify_image(p_image, p_size);
 852 }
 853 #endif