git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/emif.h>
  21 #include "board.h"
  22 #include <power/tps65218.h>
  23 #include <miiphy.h>
  24 #include <cpsw.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  29
  30 /*
  31  * Read header information from EEPROM into global structure.
  32  */
  33 static int read_eeprom(struct am43xx_board_id *header)
  34 {
  35         /* Check if baseboard eeprom is available */
  36         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  37                 printf("Could not probe the EEPROM at 0x%x\n",
  38                        CONFIG_SYS_I2C_EEPROM_ADDR);
  39                 return -ENODEV;
  40         }
  41
  42         /* read the eeprom using i2c */
  43         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  44                      sizeof(struct am43xx_board_id))) {
  45                 printf("Could not read the EEPROM\n");
  46                 return -EIO;
  47         }
  48
  49         if (header->magic != 0xEE3355AA) {
  50                 /*
  51                  * read the eeprom using i2c again,
  52                  * but use only a 1 byte address
  53                  */
  54                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  55                              sizeof(struct am43xx_board_id))) {
  56                         printf("Could not read the EEPROM at 0x%x\n",
  57                                CONFIG_SYS_I2C_EEPROM_ADDR);
  58                         return -EIO;
  59                 }
  60
  61                 if (header->magic != 0xEE3355AA) {
  62                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  63                                header->magic);
  64                         return -EINVAL;
  65                 }
  66         }
  67
  68         strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
  69         am43xx_board_name[sizeof(header->name)] = 0;
  70
  71         strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
  72         am43xx_board_rev[sizeof(header->version)] = 0;
  73
  74         return 0;
  75 }
  76
  77 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  78
  79 #define NUM_OPPS        6
  80
  81 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  82         {       /* 19.2 MHz */
  83                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 50 */
  84                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  85                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 100 */
  86                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP 120 */
  87                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP TB */
  88                 {-1, -1, -1, -1, -1, -1, -1}    /* OPP NT */
  89         },
  90         {       /* 24 MHz */
  91                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  92                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  93                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  94                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  95                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  96                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  97         },
  98         {       /* 25 MHz */
  99                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
 100                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 101                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
 102                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
 103                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
 104                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
 105         },
 106         {       /* 26 MHz */
 107                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
 108                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 109                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
 110                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
 111                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
 112                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
 113         },
 114 };
 115
 116 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
 117                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 118                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
 119                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 120                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 121 };
 122
 123 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 124                 {-1, -1, -1, -1, -1, -1, -1},   /* 19.2 MHz */
 125                 {960, 23, 5, -1, -1, -1, -1},   /* 24 MHz */
 126                 {960, 24, 5, -1, -1, -1, -1},   /* 25 MHz */
 127                 {960, 25, 5, -1, -1, -1, -1}    /* 26 MHz */
 128 };
 129
 130 const struct dpll_params epos_evm_dpll_ddr = {
 131                 266, 24, 1, -1, 1, -1, -1};
 132
 133 const struct dpll_params gp_evm_dpll_ddr = {
 134                 400, 23, 1, -1, 1, -1, -1};
 135
 136 const struct ctrl_ioregs ioregs_lpddr2 = {
 137         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 138         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 139         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 140         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 141         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 142         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 143         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 144         .emif_sdram_config_ext  = 0x1,
 145 };
 146
 147 const struct emif_regs emif_regs_lpddr2 = {
 148         .sdram_config                   = 0x808012BA,
 149         .ref_ctrl                       = 0x0000040D,
 150         .sdram_tim1                     = 0xEA86B411,
 151         .sdram_tim2                     = 0x103A094A,
 152         .sdram_tim3                     = 0x0F6BA37F,
 153         .read_idle_ctrl                 = 0x00050000,
 154         .zq_config                      = 0x50074BE4,
 155         .temp_alert_config              = 0x0,
 156         .emif_rd_wr_lvl_rmp_win         = 0x0,
 157         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 158         .emif_rd_wr_lvl_ctl             = 0x0,
 159         .emif_ddr_phy_ctlr_1            = 0x0E084006,
 160         .emif_rd_wr_exec_thresh         = 0x00000405,
 161         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 162         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 163         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 164         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 165         .emif_ddr_ext_phy_ctrl_5        = 0x00500050
 166 };
 167
 168 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 169         0x00500050,
 170         0x00350035,
 171         0x00350035,
 172         0x00350035,
 173         0x00350035,
 174         0x00350035,
 175         0x00000000,
 176         0x00000000,
 177         0x00000000,
 178         0x00000000,
 179         0x00000000,
 180         0x00000000,
 181         0x00000000,
 182         0x00000000,
 183         0x00000000,
 184         0x00000000,
 185         0x00000000,
 186         0x00000000,
 187         0x40001000,
 188         0x08102040
 189 };
 190
 191 const struct ctrl_ioregs ioregs_ddr3 = {
 192         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 193         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 194         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 195         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 196         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 197         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 198         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 199         .emif_sdram_config_ext  = 0x0143,
 200 };
 201
 202 const struct emif_regs ddr3_emif_regs_400Mhz = {
 203         .sdram_config                   = 0x638413B2,
 204         .ref_ctrl                       = 0x00000C30,
 205         .sdram_tim1                     = 0xEAAAD4DB,
 206         .sdram_tim2                     = 0x266B7FDA,
 207         .sdram_tim3                     = 0x107F8678,
 208         .read_idle_ctrl                 = 0x00050000,
 209         .zq_config                      = 0x50074BE4,
 210         .temp_alert_config              = 0x0,
 211         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 212         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 213         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 214         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 215         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 216         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 217         .emif_rd_wr_lvl_rmp_win         = 0x0,
 218         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 219         .emif_rd_wr_lvl_ctl             = 0x0,
 220         .emif_rd_wr_exec_thresh         = 0x00000405
 221 };
 222
 223 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 224 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 225         .sdram_config                   = 0x638413B2,
 226         .ref_ctrl                       = 0x00000C30,
 227         .sdram_tim1                     = 0xEAAAD4DB,
 228         .sdram_tim2                     = 0x266B7FDA,
 229         .sdram_tim3                     = 0x107F8678,
 230         .read_idle_ctrl                 = 0x00050000,
 231         .zq_config                      = 0x50074BE4,
 232         .temp_alert_config              = 0x0,
 233         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 234         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 235         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 236         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 237         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 238         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 239         .emif_rd_wr_exec_thresh         = 0x00000405
 240 };
 241
 242 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 243 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 244         .sdram_config                   = 0x638413B2,
 245         .ref_ctrl                       = 0x00000C30,
 246         .sdram_tim1                     = 0xEAAAD4DB,
 247         .sdram_tim2                     = 0x266B7FDA,
 248         .sdram_tim3                     = 0x107F8678,
 249         .read_idle_ctrl                 = 0x00050000,
 250         .zq_config                      = 0x50074BE4,
 251         .temp_alert_config              = 0x0,
 252         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 253         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 254         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 255         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 256         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 257         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 258         .emif_rd_wr_exec_thresh         = 0x00000405
 259 };
 260
 261 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 262         .sdram_config                   = 0x638413b2,
 263         .sdram_config2                  = 0x00000000,
 264         .ref_ctrl                       = 0x00000c30,
 265         .sdram_tim1                     = 0xeaaad4db,
 266         .sdram_tim2                     = 0x266b7fda,
 267         .sdram_tim3                     = 0x107f8678,
 268         .read_idle_ctrl                 = 0x00050000,
 269         .zq_config                      = 0x50074be4,
 270         .temp_alert_config              = 0x0,
 271         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 272         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 273         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 274         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 275         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 276         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 277         .emif_rd_wr_lvl_rmp_win         = 0x0,
 278         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 279         .emif_rd_wr_lvl_ctl             = 0x00000000,
 280         .emif_rd_wr_exec_thresh         = 0x00000000,
 281 };
 282
 283 const u32 ext_phy_ctrl_const_base_ddr3[] = {
 284         0x00400040,
 285         0x00350035,
 286         0x00350035,
 287         0x00350035,
 288         0x00350035,
 289         0x00350035,
 290         0x00000000,
 291         0x00000000,
 292         0x00000000,
 293         0x00000000,
 294         0x00000000,
 295         0x00340034,
 296         0x00340034,
 297         0x00340034,
 298         0x00340034,
 299         0x00340034,
 300         0x0,
 301         0x0,
 302         0x40000000,
 303         0x08102040
 304 };
 305
 306 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
 307         0x00000000,
 308         0x00000045,
 309         0x00000046,
 310         0x00000048,
 311         0x00000047,
 312         0x00000000,
 313         0x0000004C,
 314         0x00000070,
 315         0x00000085,
 316         0x000000A3,
 317         0x00000000,
 318         0x0000000C,
 319         0x00000030,
 320         0x00000045,
 321         0x00000063,
 322         0x00000000,
 323         0x0,
 324         0x0,
 325         0x40000000,
 326         0x08102040
 327 };
 328
 329 const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
 330         0x00000000,
 331         0x00000044,
 332         0x00000044,
 333         0x00000046,
 334         0x00000046,
 335         0x00000000,
 336         0x00000059,
 337         0x00000077,
 338         0x00000093,
 339         0x000000A8,
 340         0x00000000,
 341         0x00000019,
 342         0x00000037,
 343         0x00000053,
 344         0x00000068,
 345         0x00000000,
 346         0x0,
 347         0x0,
 348         0x40000000,
 349         0x08102040
 350 };
 351
 352 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
 353         /* first 5 are taken care by emif_regs */
 354         0x00700070,
 355
 356         0x00350035,
 357         0x00350035,
 358         0x00350035,
 359         0x00350035,
 360         0x00350035,
 361
 362         0x00000000,
 363         0x00000000,
 364         0x00000000,
 365         0x00000000,
 366         0x00000000,
 367
 368         0x00150015,
 369         0x00150015,
 370         0x00150015,
 371         0x00150015,
 372         0x00150015,
 373
 374         0x00800080,
 375         0x00800080,
 376
 377         0x40000000,
 378
 379         0x08102040,
 380
 381         0x00000000,
 382         0x00000000,
 383         0x00000000,
 384         0x00000000,
 385         0x00000000,
 386         0x00000000,
 387         0x00000000,
 388         0x00000000,
 389         0x00000000,
 390         0x00000000,
 391         0x00000000,
 392 };
 393
 394 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 395 {
 396         if (board_is_eposevm()) {
 397                 *regs = ext_phy_ctrl_const_base_lpddr2;
 398                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 399         } else if (board_is_evm_14_or_later()) {
 400                 *regs = ext_phy_ctrl_const_base_ddr3_production;
 401                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
 402         } else if (board_is_evm_12_or_later()) {
 403                 *regs = ext_phy_ctrl_const_base_ddr3_beta;
 404                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
 405         } else if (board_is_gpevm()) {
 406                 *regs = ext_phy_ctrl_const_base_ddr3;
 407                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
 408         } else if (board_is_sk()) {
 409                 *regs = ext_phy_ctrl_const_base_ddr3_sk;
 410                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
 411         }
 412
 413         return;
 414 }
 415
 416 const struct dpll_params *get_dpll_ddr_params(void)
 417 {
 418         if (board_is_eposevm())
 419                 return &epos_evm_dpll_ddr;
 420         else if (board_is_gpevm() || board_is_sk())
 421                 return &gp_evm_dpll_ddr;
 422
 423         printf(" Board '%s' not supported\n", am43xx_board_name);
 424         return NULL;
 425 }
 426
 427 /*
 428  * get_sys_clk_index : returns the index of the sys_clk read from
 429  *                      ctrl status register. This value is either
 430  *                      read from efuse or sysboot pins.
 431  */
 432 static u32 get_sys_clk_index(void)
 433 {
 434         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 435         u32 ind = readl(&ctrl->statusreg), src;
 436
 437         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 438         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 439                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 440                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 441         else /* Value read from SYS BOOT pins */
 442                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 443                         CTRL_SYSBOOT_15_14_SHIFT);
 444 }
 445
 446 /*
 447  * get_opp_offset:
 448  * Returns the index for safest OPP of the device to boot.
 449  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 450  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 451  * This data is read from dev_attribute register which is e-fused.
 452  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 453  * OPP available. Lowest OPP starts with min_off. So returning the
 454  * bit with rightmost '0'.
 455  */
 456 static int get_opp_offset(int max_off, int min_off)
 457 {
 458         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 459         int opp, offset, i;
 460
 461         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 462         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 463
 464         for (i = max_off; i >= min_off; i--) {
 465                 offset = opp & (1 << i);
 466                 if (!offset)
 467                         return i;
 468         }
 469
 470         return min_off;
 471 }
 472
 473 const struct dpll_params *get_dpll_mpu_params(void)
 474 {
 475         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 476         u32 ind = get_sys_clk_index();
 477
 478         return &dpll_mpu[ind][opp];
 479 }
 480
 481 const struct dpll_params *get_dpll_core_params(void)
 482 {
 483         int ind = get_sys_clk_index();
 484
 485         return &dpll_core[ind];
 486 }
 487
 488 const struct dpll_params *get_dpll_per_params(void)
 489 {
 490         int ind = get_sys_clk_index();
 491
 492         return &dpll_per[ind];
 493 }
 494
 495 void scale_vcores(void)
 496 {
 497         const struct dpll_params *mpu_params;
 498         int mpu_vdd;
 499         struct am43xx_board_id header;
 500
 501         enable_i2c0_pin_mux();
 502         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 503         if (read_eeprom(&header) < 0)
 504                 puts("Could not get board ID.\n");
 505
 506         /* Get the frequency */
 507         mpu_params = get_dpll_mpu_params();
 508
 509         if (i2c_probe(TPS65218_CHIP_PM))
 510                 return;
 511
 512         if (mpu_params->m == 1000) {
 513                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 514         } else if (mpu_params->m == 600) {
 515                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 516         } else {
 517                 puts("Unknown MPU clock, not scaling\n");
 518                 return;
 519         }
 520
 521         /* Set DCDC1 (CORE) voltage to 1.1V */
 522         if (tps65218_voltage_update(TPS65218_DCDC1,
 523                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 524                 puts("tps65218_voltage_update failure\n");
 525                 return;
 526         }
 527
 528         /* Set DCDC2 (MPU) voltage */
 529         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 530                 puts("tps65218_voltage_update failure\n");
 531                 return;
 532         }
 533 }
 534
 535 void set_uart_mux_conf(void)
 536 {
 537         enable_uart0_pin_mux();
 538 }
 539
 540 void set_mux_conf_regs(void)
 541 {
 542         enable_board_pin_mux();
 543 }
 544
 545 static void enable_vtt_regulator(void)
 546 {
 547         u32 temp;
 548
 549         /* enable module */
 550         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 551
 552         /* enable output for GPIO5_7 */
 553         writel(GPIO_SETDATAOUT(7),
 554                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 555         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 556         temp = temp & ~(GPIO_OE_ENABLE(7));
 557         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 558 }
 559
 560 void sdram_init(void)
 561 {
 562         /*
 563          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 564          * GP EMV has 1GB DDR3 connected to EMIF
 565          * along with VTT regulator.
 566          */
 567         if (board_is_eposevm()) {
 568                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 569         } else if (board_is_evm_14_or_later()) {
 570                 enable_vtt_regulator();
 571                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 572                            &ddr3_emif_regs_400Mhz_production, 0);
 573         } else if (board_is_evm_12_or_later()) {
 574                 enable_vtt_regulator();
 575                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 576                            &ddr3_emif_regs_400Mhz_beta, 0);
 577         } else if (board_is_gpevm()) {
 578                 enable_vtt_regulator();
 579                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 580                            &ddr3_emif_regs_400Mhz, 0);
 581         } else if (board_is_sk()) {
 582                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 583                            &ddr3_sk_emif_regs_400Mhz, 0);
 584         }
 585 }
 586 #endif
 587
 588 int board_init(void)
 589 {
 590         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 591
 592         return 0;
 593 }
 594
 595 #ifdef CONFIG_BOARD_LATE_INIT
 596 int board_late_init(void)
 597 {
 598 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 599         char safe_string[HDR_NAME_LEN + 1];
 600         struct am43xx_board_id header;
 601
 602         if (read_eeprom(&header) < 0)
 603                 puts("Could not get board ID.\n");
 604
 605         /* Now set variables based on the header. */
 606         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 607         safe_string[sizeof(header.name)] = 0;
 608         setenv("board_name", safe_string);
 609
 610         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 611         safe_string[sizeof(header.version)] = 0;
 612         setenv("board_rev", safe_string);
 613 #endif
 614         return 0;
 615 }
 616 #endif
 617
 618 #ifdef CONFIG_DRIVER_TI_CPSW
 619
 620 static void cpsw_control(int enabled)
 621 {
 622         /* Additional controls can be added here */
 623         return;
 624 }
 625
 626 static struct cpsw_slave_data cpsw_slaves[] = {
 627         {
 628                 .slave_reg_ofs  = 0x208,
 629                 .sliver_reg_ofs = 0xd80,
 630                 .phy_addr       = 16,
 631         },
 632         {
 633                 .slave_reg_ofs  = 0x308,
 634                 .sliver_reg_ofs = 0xdc0,
 635                 .phy_addr       = 1,
 636         },
 637 };
 638
 639 static struct cpsw_platform_data cpsw_data = {
 640         .mdio_base              = CPSW_MDIO_BASE,
 641         .cpsw_base              = CPSW_BASE,
 642         .mdio_div               = 0xff,
 643         .channels               = 8,
 644         .cpdma_reg_ofs          = 0x800,
 645         .slaves                 = 1,
 646         .slave_data             = cpsw_slaves,
 647         .ale_reg_ofs            = 0xd00,
 648         .ale_entries            = 1024,
 649         .host_port_reg_ofs      = 0x108,
 650         .hw_stats_reg_ofs       = 0x900,
 651         .bd_ram_ofs             = 0x2000,
 652         .mac_control            = (1 << 5),
 653         .control                = cpsw_control,
 654         .host_port_num          = 0,
 655         .version                = CPSW_CTRL_VERSION_2,
 656 };
 657
 658 int board_eth_init(bd_t *bis)
 659 {
 660         int rv;
 661         uint8_t mac_addr[6];
 662         uint32_t mac_hi, mac_lo;
 663
 664         /* try reading mac address from efuse */
 665         mac_lo = readl(&cdev->macid0l);
 666         mac_hi = readl(&cdev->macid0h);
 667         mac_addr[0] = mac_hi & 0xFF;
 668         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 669         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 670         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 671         mac_addr[4] = mac_lo & 0xFF;
 672         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 673
 674         if (!getenv("ethaddr")) {
 675                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 676                 if (is_valid_ether_addr(mac_addr))
 677                         eth_setenv_enetaddr("ethaddr", mac_addr);
 678         }
 679
 680         mac_lo = readl(&cdev->macid1l);
 681         mac_hi = readl(&cdev->macid1h);
 682         mac_addr[0] = mac_hi & 0xFF;
 683         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 684         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 685         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 686         mac_addr[4] = mac_lo & 0xFF;
 687         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 688
 689         if (!getenv("eth1addr")) {
 690                 if (is_valid_ether_addr(mac_addr))
 691                         eth_setenv_enetaddr("eth1addr", mac_addr);
 692         }
 693
 694         if (board_is_eposevm()) {
 695                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 696                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 697                 cpsw_slaves[0].phy_addr = 16;
 698         } else if (board_is_sk()) {
 699                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 700                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 701                 cpsw_slaves[0].phy_addr = 4;
 702                 cpsw_slaves[1].phy_addr = 5;
 703         } else {
 704                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 705                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 706                 cpsw_slaves[0].phy_addr = 0;
 707         }
 708
 709         rv = cpsw_register(&cpsw_data);
 710         if (rv < 0)
 711                 printf("Error %d registering CPSW switch\n", rv);
 712
 713         return rv;
 714 }
 715 #endif