4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
22 #include <power/pmic.h>
23 #include <power/tps65218.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
32 * Read header information from EEPROM into global structure.
34 static int read_eeprom(struct am43xx_board_id *header)
36 /* Check if baseboard eeprom is available */
37 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
38 printf("Could not probe the EEPROM at 0x%x\n",
39 CONFIG_SYS_I2C_EEPROM_ADDR);
43 /* read the eeprom using i2c */
44 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
45 sizeof(struct am43xx_board_id))) {
46 printf("Could not read the EEPROM\n");
50 if (header->magic != 0xEE3355AA) {
52 * read the eeprom using i2c again,
53 * but use only a 1 byte address
55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
56 sizeof(struct am43xx_board_id))) {
57 printf("Could not read the EEPROM at 0x%x\n",
58 CONFIG_SYS_I2C_EEPROM_ADDR);
62 if (header->magic != 0xEE3355AA) {
63 printf("Incorrect magic number (0x%x) in EEPROM\n",
69 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
70 am43xx_board_name[sizeof(header->name)] = 0;
72 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
73 am43xx_board_rev[sizeof(header->version)] = 0;
78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
82 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
84 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
86 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
87 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
88 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
89 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
92 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
93 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
94 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
95 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
96 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
97 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
100 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
101 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
102 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
103 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
104 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
105 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
108 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
109 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
110 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
111 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
112 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
113 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
117 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
118 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
119 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
120 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
121 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
124 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
125 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
126 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
127 {32, 0, 8, -1, -1, -1, -1}, /* 25 MHz */
128 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
131 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
132 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
133 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
134 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
135 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
138 const struct dpll_params gp_evm_dpll_ddr = {
139 50, 2, 1, -1, 2, -1, -1};
141 const struct ctrl_ioregs ioregs_lpddr2 = {
142 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
143 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
144 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
145 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
146 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
147 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
148 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
149 .emif_sdram_config_ext = 0x1,
152 const struct emif_regs emif_regs_lpddr2 = {
153 .sdram_config = 0x808012BA,
154 .ref_ctrl = 0x0000040D,
155 .sdram_tim1 = 0xEA86B411,
156 .sdram_tim2 = 0x103A094A,
157 .sdram_tim3 = 0x0F6BA37F,
158 .read_idle_ctrl = 0x00050000,
159 .zq_config = 0x50074BE4,
160 .temp_alert_config = 0x0,
161 .emif_rd_wr_lvl_rmp_win = 0x0,
162 .emif_rd_wr_lvl_rmp_ctl = 0x0,
163 .emif_rd_wr_lvl_ctl = 0x0,
164 .emif_ddr_phy_ctlr_1 = 0x0E284006,
165 .emif_rd_wr_exec_thresh = 0x80000405,
166 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
167 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
168 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
169 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
170 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
171 .emif_prio_class_serv_map = 0x80000001,
172 .emif_connect_id_serv_1_map = 0x80000094,
173 .emif_connect_id_serv_2_map = 0x00000000,
174 .emif_cos_config = 0x000FFFFF
177 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
200 const struct ctrl_ioregs ioregs_ddr3 = {
201 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
202 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
203 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
204 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
205 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
206 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
207 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
208 .emif_sdram_config_ext = 0xc163,
211 const struct emif_regs ddr3_emif_regs_400Mhz = {
212 .sdram_config = 0x638413B2,
213 .ref_ctrl = 0x00000C30,
214 .sdram_tim1 = 0xEAAAD4DB,
215 .sdram_tim2 = 0x266B7FDA,
216 .sdram_tim3 = 0x107F8678,
217 .read_idle_ctrl = 0x00050000,
218 .zq_config = 0x50074BE4,
219 .temp_alert_config = 0x0,
220 .emif_ddr_phy_ctlr_1 = 0x0E004008,
221 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
222 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
223 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
224 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
225 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
226 .emif_rd_wr_lvl_rmp_win = 0x0,
227 .emif_rd_wr_lvl_rmp_ctl = 0x0,
228 .emif_rd_wr_lvl_ctl = 0x0,
229 .emif_rd_wr_exec_thresh = 0x80000405,
230 .emif_prio_class_serv_map = 0x80000001,
231 .emif_connect_id_serv_1_map = 0x80000094,
232 .emif_connect_id_serv_2_map = 0x00000000,
233 .emif_cos_config = 0x000FFFFF
236 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
237 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
238 .sdram_config = 0x638413B2,
239 .ref_ctrl = 0x00000C30,
240 .sdram_tim1 = 0xEAAAD4DB,
241 .sdram_tim2 = 0x266B7FDA,
242 .sdram_tim3 = 0x107F8678,
243 .read_idle_ctrl = 0x00050000,
244 .zq_config = 0x50074BE4,
245 .temp_alert_config = 0x0,
246 .emif_ddr_phy_ctlr_1 = 0x0E004008,
247 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
248 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
249 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
250 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
251 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
252 .emif_rd_wr_exec_thresh = 0x80000405,
253 .emif_prio_class_serv_map = 0x80000001,
254 .emif_connect_id_serv_1_map = 0x80000094,
255 .emif_connect_id_serv_2_map = 0x00000000,
256 .emif_cos_config = 0x000FFFFF
259 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
260 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
261 .sdram_config = 0x638413B2,
262 .ref_ctrl = 0x00000C30,
263 .sdram_tim1 = 0xEAAAD4DB,
264 .sdram_tim2 = 0x266B7FDA,
265 .sdram_tim3 = 0x107F8678,
266 .read_idle_ctrl = 0x00050000,
267 .zq_config = 0x50074BE4,
268 .temp_alert_config = 0x0,
269 .emif_ddr_phy_ctlr_1 = 0x0E004008,
270 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
271 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
272 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
273 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
274 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
275 .emif_rd_wr_exec_thresh = 0x80000405,
276 .emif_prio_class_serv_map = 0x80000001,
277 .emif_connect_id_serv_1_map = 0x80000094,
278 .emif_connect_id_serv_2_map = 0x00000000,
279 .emif_cos_config = 0x000FFFFF
282 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
283 .sdram_config = 0x638413b2,
284 .sdram_config2 = 0x00000000,
285 .ref_ctrl = 0x00000c30,
286 .sdram_tim1 = 0xeaaad4db,
287 .sdram_tim2 = 0x266b7fda,
288 .sdram_tim3 = 0x107f8678,
289 .read_idle_ctrl = 0x00050000,
290 .zq_config = 0x50074be4,
291 .temp_alert_config = 0x0,
292 .emif_ddr_phy_ctlr_1 = 0x0e084008,
293 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
294 .emif_ddr_ext_phy_ctrl_2 = 0x89,
295 .emif_ddr_ext_phy_ctrl_3 = 0x90,
296 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
297 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
298 .emif_rd_wr_lvl_rmp_win = 0x0,
299 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
300 .emif_rd_wr_lvl_ctl = 0x00000000,
301 .emif_rd_wr_exec_thresh = 0x80000000,
302 .emif_prio_class_serv_map = 0x80000001,
303 .emif_connect_id_serv_1_map = 0x80000094,
304 .emif_connect_id_serv_2_map = 0x00000000,
305 .emif_cos_config = 0x000FFFFF
308 const u32 ext_phy_ctrl_const_base_ddr3[] = {
331 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
354 const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
377 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
378 /* first 5 are taken care by emif_regs */
419 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
421 if (board_is_eposevm()) {
422 *regs = ext_phy_ctrl_const_base_lpddr2;
423 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
424 } else if (board_is_evm_14_or_later()) {
425 *regs = ext_phy_ctrl_const_base_ddr3_production;
426 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
427 } else if (board_is_evm_12_or_later()) {
428 *regs = ext_phy_ctrl_const_base_ddr3_beta;
429 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
430 } else if (board_is_gpevm()) {
431 *regs = ext_phy_ctrl_const_base_ddr3;
432 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
433 } else if (board_is_sk()) {
434 *regs = ext_phy_ctrl_const_base_ddr3_sk;
435 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
442 * get_sys_clk_index : returns the index of the sys_clk read from
443 * ctrl status register. This value is either
444 * read from efuse or sysboot pins.
446 static u32 get_sys_clk_index(void)
448 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
449 u32 ind = readl(&ctrl->statusreg), src;
451 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
452 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
453 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
454 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
455 else /* Value read from SYS BOOT pins */
456 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
457 CTRL_SYSBOOT_15_14_SHIFT);
460 const struct dpll_params *get_dpll_ddr_params(void)
462 int ind = get_sys_clk_index();
464 if (board_is_eposevm())
465 return &epos_evm_dpll_ddr[ind];
466 else if (board_is_gpevm() || board_is_sk())
467 return &gp_evm_dpll_ddr;
469 printf(" Board '%s' not supported\n", am43xx_board_name);
476 * Returns the index for safest OPP of the device to boot.
477 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
478 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
479 * This data is read from dev_attribute register which is e-fused.
480 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
481 * OPP available. Lowest OPP starts with min_off. So returning the
482 * bit with rightmost '0'.
484 static int get_opp_offset(int max_off, int min_off)
486 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
489 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
490 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
492 for (i = max_off; i >= min_off; i--) {
493 offset = opp & (1 << i);
501 const struct dpll_params *get_dpll_mpu_params(void)
503 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
504 u32 ind = get_sys_clk_index();
506 return &dpll_mpu[ind][opp];
509 const struct dpll_params *get_dpll_core_params(void)
511 int ind = get_sys_clk_index();
513 return &dpll_core[ind];
516 const struct dpll_params *get_dpll_per_params(void)
518 int ind = get_sys_clk_index();
520 return &dpll_per[ind];
523 void scale_vcores(void)
525 const struct dpll_params *mpu_params;
527 struct am43xx_board_id header;
529 enable_i2c0_pin_mux();
530 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
531 if (read_eeprom(&header) < 0)
532 puts("Could not get board ID.\n");
534 /* Get the frequency */
535 mpu_params = get_dpll_mpu_params();
537 if (i2c_probe(TPS65218_CHIP_PM))
540 if (mpu_params->m == 1000) {
541 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
542 } else if (mpu_params->m == 600) {
543 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
545 puts("Unknown MPU clock, not scaling\n");
549 /* Set DCDC1 (CORE) voltage to 1.1V */
550 if (tps65218_voltage_update(TPS65218_DCDC1,
551 TPS65218_DCDC_VOLT_SEL_1100MV)) {
552 puts("tps65218_voltage_update failure\n");
556 /* Set DCDC2 (MPU) voltage */
557 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
558 puts("tps65218_voltage_update failure\n");
563 void set_uart_mux_conf(void)
565 enable_uart0_pin_mux();
568 void set_mux_conf_regs(void)
570 enable_board_pin_mux();
573 static void enable_vtt_regulator(void)
578 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
580 /* enable output for GPIO5_7 */
581 writel(GPIO_SETDATAOUT(7),
582 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
583 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
584 temp = temp & ~(GPIO_OE_ENABLE(7));
585 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
588 void sdram_init(void)
591 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
592 * GP EMV has 1GB DDR3 connected to EMIF
593 * along with VTT regulator.
595 if (board_is_eposevm()) {
596 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
597 } else if (board_is_evm_14_or_later()) {
598 enable_vtt_regulator();
599 config_ddr(0, &ioregs_ddr3, NULL, NULL,
600 &ddr3_emif_regs_400Mhz_production, 0);
601 } else if (board_is_evm_12_or_later()) {
602 enable_vtt_regulator();
603 config_ddr(0, &ioregs_ddr3, NULL, NULL,
604 &ddr3_emif_regs_400Mhz_beta, 0);
605 } else if (board_is_gpevm()) {
606 enable_vtt_regulator();
607 config_ddr(0, &ioregs_ddr3, NULL, NULL,
608 &ddr3_emif_regs_400Mhz, 0);
609 } else if (board_is_sk()) {
610 config_ddr(400, &ioregs_ddr3, NULL, NULL,
611 &ddr3_sk_emif_regs_400Mhz, 0);
616 /* setup board specific PMIC */
617 int power_init_board(void)
621 power_tps65218_init(I2C_PMIC);
622 p = pmic_get("TPS65218_PMIC");
623 if (p && !pmic_probe(p))
624 puts("PMIC: TPS65218\n");
631 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
632 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
633 modena_init0_bw_integer, modena_init0_watermark_0;
635 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
638 /* Clear all important bits for DSS errata that may need to be tweaked*/
639 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
640 MREQPRIO_0_SAB_INIT0_MASK;
642 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
644 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
645 BW_LIMITER_BW_FRAC_MASK;
647 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
648 BW_LIMITER_BW_INT_MASK;
650 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
651 BW_LIMITER_BW_WATERMARK_MASK;
653 /* Setting MReq Priority of the DSS*/
657 * Set L3 Fast Configuration Register
658 * Limiting bandwith for ARM core to 700 MBPS
660 modena_init0_bw_fractional |= 0x10;
661 modena_init0_bw_integer |= 0x3;
663 writel(mreqprio_0, &cdev->mreqprio_0);
664 writel(mreqprio_1, &cdev->mreqprio_1);
666 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
667 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
668 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
673 #ifdef CONFIG_BOARD_LATE_INIT
674 int board_late_init(void)
676 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
677 char safe_string[HDR_NAME_LEN + 1];
678 struct am43xx_board_id header;
680 if (read_eeprom(&header) < 0)
681 puts("Could not get board ID.\n");
683 /* Now set variables based on the header. */
684 strncpy(safe_string, (char *)header.name, sizeof(header.name));
685 safe_string[sizeof(header.name)] = 0;
686 setenv("board_name", safe_string);
688 strncpy(safe_string, (char *)header.version, sizeof(header.version));
689 safe_string[sizeof(header.version)] = 0;
690 setenv("board_rev", safe_string);
696 #ifdef CONFIG_DRIVER_TI_CPSW
698 static void cpsw_control(int enabled)
700 /* Additional controls can be added here */
704 static struct cpsw_slave_data cpsw_slaves[] = {
706 .slave_reg_ofs = 0x208,
707 .sliver_reg_ofs = 0xd80,
711 .slave_reg_ofs = 0x308,
712 .sliver_reg_ofs = 0xdc0,
717 static struct cpsw_platform_data cpsw_data = {
718 .mdio_base = CPSW_MDIO_BASE,
719 .cpsw_base = CPSW_BASE,
722 .cpdma_reg_ofs = 0x800,
724 .slave_data = cpsw_slaves,
725 .ale_reg_ofs = 0xd00,
727 .host_port_reg_ofs = 0x108,
728 .hw_stats_reg_ofs = 0x900,
729 .bd_ram_ofs = 0x2000,
730 .mac_control = (1 << 5),
731 .control = cpsw_control,
733 .version = CPSW_CTRL_VERSION_2,
736 int board_eth_init(bd_t *bis)
740 uint32_t mac_hi, mac_lo;
742 /* try reading mac address from efuse */
743 mac_lo = readl(&cdev->macid0l);
744 mac_hi = readl(&cdev->macid0h);
745 mac_addr[0] = mac_hi & 0xFF;
746 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
747 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
748 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
749 mac_addr[4] = mac_lo & 0xFF;
750 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
752 if (!getenv("ethaddr")) {
753 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
754 if (is_valid_ether_addr(mac_addr))
755 eth_setenv_enetaddr("ethaddr", mac_addr);
758 mac_lo = readl(&cdev->macid1l);
759 mac_hi = readl(&cdev->macid1h);
760 mac_addr[0] = mac_hi & 0xFF;
761 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
762 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
763 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
764 mac_addr[4] = mac_lo & 0xFF;
765 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
767 if (!getenv("eth1addr")) {
768 if (is_valid_ether_addr(mac_addr))
769 eth_setenv_enetaddr("eth1addr", mac_addr);
772 if (board_is_eposevm()) {
773 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
774 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
775 cpsw_slaves[0].phy_addr = 16;
776 } else if (board_is_sk()) {
777 writel(RGMII_MODE_ENABLE, &cdev->miisel);
778 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
779 cpsw_slaves[0].phy_addr = 4;
780 cpsw_slaves[1].phy_addr = 5;
782 writel(RGMII_MODE_ENABLE, &cdev->miisel);
783 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
784 cpsw_slaves[0].phy_addr = 0;
787 rv = cpsw_register(&cpsw_data);
789 printf("Error %d registering CPSW switch\n", rv);