2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
40 #define board_is_am572x_evm() board_ti_is("AM572PM_")
41 #define board_is_am572x_evm_reva3() \
42 (board_ti_is("AM572PM_") && \
43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
44 #define board_is_am572x_idk() board_ti_is("AM572IDK")
45 #define board_is_am571x_idk() board_ti_is("AM571IDK")
47 #ifdef CONFIG_DRIVER_TI_CPSW
51 DECLARE_GLOBAL_DATA_PTR;
53 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
55 #define GPIO_DDR_VTT_EN 203
57 #define SYSINFO_BOARD_NAME_MAX_LEN 45
59 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
60 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
62 const struct omap_sysinfo sysinfo = {
63 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
66 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
67 .dmm_lisa_map_3 = 0x80740300,
71 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
72 .dmm_lisa_map_3 = 0x80640100,
76 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
78 if (board_is_am571x_idk())
79 *dmm_lisa_regs = &am571x_idk_lisa_regs;
81 *dmm_lisa_regs = &beagle_x15_lisa_regs;
84 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
85 .sdram_config_init = 0x61851b32,
86 .sdram_config = 0x61851b32,
87 .sdram_config2 = 0x08000000,
88 .ref_ctrl = 0x000040F1,
89 .ref_ctrl_final = 0x00001035,
90 .sdram_tim1 = 0xcccf36ab,
91 .sdram_tim2 = 0x308f7fda,
92 .sdram_tim3 = 0x409f88a8,
93 .read_idle_ctrl = 0x00050000,
94 .zq_config = 0x5007190b,
95 .temp_alert_config = 0x00000000,
96 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
97 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
98 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
99 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
100 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
101 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
102 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
103 .emif_rd_wr_lvl_rmp_win = 0x00000000,
104 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
105 .emif_rd_wr_lvl_ctl = 0x00000000,
106 .emif_rd_wr_exec_thresh = 0x00000305
109 /* Ext phy ctrl regs 1-35 */
110 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
148 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
149 .sdram_config_init = 0x61851b32,
150 .sdram_config = 0x61851b32,
151 .sdram_config2 = 0x08000000,
152 .ref_ctrl = 0x000040F1,
153 .ref_ctrl_final = 0x00001035,
154 .sdram_tim1 = 0xcccf36b3,
155 .sdram_tim2 = 0x308f7fda,
156 .sdram_tim3 = 0x407f88a8,
157 .read_idle_ctrl = 0x00050000,
158 .zq_config = 0x5007190b,
159 .temp_alert_config = 0x00000000,
160 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
161 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
162 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
163 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
164 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
165 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
166 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
167 .emif_rd_wr_lvl_rmp_win = 0x00000000,
168 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
169 .emif_rd_wr_lvl_ctl = 0x00000000,
170 .emif_rd_wr_exec_thresh = 0x00000305
173 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
211 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
215 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
218 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
223 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
227 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
228 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
231 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
232 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
237 struct vcores_data beagle_x15_volts = {
238 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
239 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
240 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
241 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
242 .mpu.pmic = &tps659038,
243 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
245 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
246 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
247 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
248 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
249 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
250 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
251 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
252 .eve.addr = TPS659038_REG_ADDR_SMPS45,
253 .eve.pmic = &tps659038,
254 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
256 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
257 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
258 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
259 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
260 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
261 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
262 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
263 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
264 .gpu.pmic = &tps659038,
265 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
267 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
268 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
269 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
270 .core.addr = TPS659038_REG_ADDR_SMPS6,
271 .core.pmic = &tps659038,
273 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
274 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
275 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
276 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
277 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
278 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
279 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
280 .iva.addr = TPS659038_REG_ADDR_SMPS45,
281 .iva.pmic = &tps659038,
282 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
285 struct vcores_data am572x_idk_volts = {
286 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
287 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
288 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
289 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
290 .mpu.pmic = &tps659038,
291 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
293 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
294 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
295 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
296 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
297 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
298 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
299 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
300 .eve.addr = TPS659038_REG_ADDR_SMPS45,
301 .eve.pmic = &tps659038,
302 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
304 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
305 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
306 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
307 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
308 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
309 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
310 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
311 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
312 .gpu.pmic = &tps659038,
313 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
315 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
316 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
317 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
318 .core.addr = TPS659038_REG_ADDR_SMPS7,
319 .core.pmic = &tps659038,
321 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
322 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
323 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
324 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
325 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
326 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
327 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
328 .iva.addr = TPS659038_REG_ADDR_SMPS8,
329 .iva.pmic = &tps659038,
330 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
333 int get_voltrail_opp(int rail_offset)
337 switch (rail_offset) {
348 opp = DRA7_DSPEVE_OPP;
361 #ifdef CONFIG_SPL_BUILD
362 /* No env to setup for SPL */
363 static inline void setup_board_eeprom_env(void) { }
365 /* Override function to read eeprom information */
366 void do_board_detect(void)
370 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
371 CONFIG_EEPROM_CHIP_ADDRESS);
373 printf("ti_i2c_eeprom_init failed %d\n", rc);
376 #else /* CONFIG_SPL_BUILD */
378 /* Override function to read eeprom information: actual i2c read done by SPL*/
379 void do_board_detect(void)
384 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
385 CONFIG_EEPROM_CHIP_ADDRESS);
387 printf("ti_i2c_eeprom_init failed %d\n", rc);
390 bname = "BeagleBoard X15";
391 else if (board_is_am572x_evm())
392 bname = "AM572x EVM";
393 else if (board_is_am572x_idk())
394 bname = "AM572x IDK";
395 else if (board_is_am571x_idk())
396 bname = "AM571x IDK";
399 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
400 "Board: %s REV %s\n", bname, board_ti_get_rev());
403 static void setup_board_eeprom_env(void)
405 char *name = "beagle_x15";
408 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
409 CONFIG_EEPROM_CHIP_ADDRESS);
413 if (board_is_x15()) {
414 if (board_is_x15_revb1())
415 name = "beagle_x15_revb1";
418 } else if (board_is_am572x_evm()) {
419 if (board_is_am572x_evm_reva3())
420 name = "am57xx_evm_reva3";
423 } else if (board_is_am572x_idk()) {
425 } else if (board_is_am571x_idk()) {
428 printf("Unidentified board claims %s in eeprom header\n",
429 board_ti_get_name());
433 set_board_info_env(name);
436 #endif /* CONFIG_SPL_BUILD */
438 void vcores_init(void)
440 if (board_is_am572x_idk())
441 *omap_vcores = &am572x_idk_volts;
443 *omap_vcores = &beagle_x15_volts;
446 void hw_data_init(void)
448 *prcm = &dra7xx_prcm;
449 *dplls_data = &dra7xx_dplls;
450 *ctrl = &dra7xx_ctrl;
453 bool am571x_idk_needs_lcd(void)
457 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
458 if (gpio_get_value(GPIO_ETH_LCD))
463 gpio_free(GPIO_ETH_LCD);
471 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
476 int board_late_init(void)
480 setup_board_eeprom_env();
484 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
485 * This is the POWERHOLD-in-Low behavior.
487 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
490 * Default FIT boot on HS devices. Non FIT images are not allowed
493 if (get_device_type() == HS_DEVICE)
494 setenv("boot_fit", "1");
497 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
498 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
499 * PMIC Power off. So to be on the safer side set it back
500 * to POWERHOLD mode irrespective of the current state.
502 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
504 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
505 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
508 omap_die_id_serial();
510 /* TBD: Add LCD panel detection once information is available */
511 if (am571x_idk_needs_lcd())
512 idk_lcd = "osd101t2045"; /* Default to legacy LCD */
515 setenv("idk_lcd", idk_lcd);
517 #if !defined(CONFIG_SPL_BUILD)
518 board_ti_set_ethaddr(2);
524 void set_muxconf_regs(void)
526 do_set_mux32((*ctrl)->control_padconf_core_base,
527 early_padconf, ARRAY_SIZE(early_padconf));
530 #ifdef CONFIG_IODELAY_RECALIBRATION
531 void recalibrate_iodelay(void)
533 const struct pad_conf_entry *pconf;
534 const struct iodelay_cfg_entry *iod;
535 int pconf_sz, iod_sz;
538 if (board_is_am572x_idk()) {
539 pconf = core_padconf_array_essential_am572x_idk;
540 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
541 iod = iodelay_cfg_array_am572x_idk;
542 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
543 } else if (board_is_am571x_idk()) {
544 pconf = core_padconf_array_essential_am571x_idk;
545 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
546 iod = iodelay_cfg_array_am571x_idk;
547 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
549 /* Common for X15/GPEVM */
550 pconf = core_padconf_array_essential_x15;
551 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
552 /* There never was an SR1.0 X15.. So.. */
553 if (omap_revision() == DRA752_ES1_1) {
554 iod = iodelay_cfg_array_x15_sr1_1;
555 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
557 /* Since full production should switch to SR2.0 */
558 iod = iodelay_cfg_array_x15_sr2_0;
559 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
563 /* Setup I/O isolation */
564 ret = __recalibrate_iodelay_start();
568 /* Do the muxing here */
569 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
571 /* Now do the weird minor deltas that should be safe */
572 if (board_is_x15() || board_is_am572x_evm()) {
573 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
574 pconf = core_padconf_array_delta_x15_sr2_0;
575 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
577 pconf = core_padconf_array_delta_x15_sr1_1;
578 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
580 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
583 if (board_is_am571x_idk()) {
584 if (am571x_idk_needs_lcd()) {
585 pconf = core_padconf_array_vout_am571x_idk;
586 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
588 pconf = core_padconf_array_icss1eth_am571x_idk;
589 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
591 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
594 /* Setup IOdelay configuration */
595 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
597 /* Closeup.. remove isolation */
598 __recalibrate_iodelay_end(ret);
602 #if defined(CONFIG_GENERIC_MMC)
603 int board_mmc_init(bd_t *bis)
605 omap_mmc_init(0, 0, 0, -1, -1);
606 omap_mmc_init(1, 0, 0, -1, -1);
611 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
612 int spl_start_uboot(void)
614 /* break into full u-boot on 'c' */
615 if (serial_tstc() && serial_getc() == 'c')
618 #ifdef CONFIG_SPL_ENV_SUPPORT
621 if (getenv_yesno("boot_os") != 1)
629 #ifdef CONFIG_USB_DWC3
630 static struct dwc3_device usb_otg_ss2 = {
631 .maximum_speed = USB_SPEED_HIGH,
632 .base = DRA7_USB_OTG_SS2_BASE,
633 .tx_fifo_resize = false,
637 static struct dwc3_omap_device usb_otg_ss2_glue = {
638 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
639 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
643 static struct ti_usb_phy_device usb_phy2_device = {
644 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
648 int usb_gadget_handle_interrupts(int index)
652 status = dwc3_omap_uboot_interrupt_status(index);
654 dwc3_uboot_handle_interrupt(index);
658 #endif /* CONFIG_USB_DWC3 */
660 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
661 int board_usb_init(int index, enum usb_init_type init)
663 enable_usb_clocks(index);
666 if (init == USB_INIT_DEVICE) {
667 printf("port %d can't be used as device\n", index);
668 disable_usb_clocks(index);
673 if (init == USB_INIT_DEVICE) {
674 #ifdef CONFIG_USB_DWC3
675 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
676 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
677 ti_usb_phy_uboot_init(&usb_phy2_device);
678 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
679 dwc3_uboot_init(&usb_otg_ss2);
682 printf("port %d can't be used as host\n", index);
683 disable_usb_clocks(index);
689 printf("Invalid Controller Index\n");
695 int board_usb_cleanup(int index, enum usb_init_type init)
697 #ifdef CONFIG_USB_DWC3
701 if (init == USB_INIT_DEVICE) {
702 ti_usb_phy_uboot_exit(index);
703 dwc3_uboot_exit(index);
704 dwc3_omap_uboot_exit(index);
708 printf("Invalid Controller Index\n");
711 disable_usb_clocks(index);
714 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
716 #ifdef CONFIG_DRIVER_TI_CPSW
718 /* Delay value to add to calibrated value */
719 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
720 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
721 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
722 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
723 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
724 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
725 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
726 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
727 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
728 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
730 static void cpsw_control(int enabled)
732 /* VTP can be added here */
735 static struct cpsw_slave_data cpsw_slaves[] = {
737 .slave_reg_ofs = 0x208,
738 .sliver_reg_ofs = 0xd80,
742 .slave_reg_ofs = 0x308,
743 .sliver_reg_ofs = 0xdc0,
748 static struct cpsw_platform_data cpsw_data = {
749 .mdio_base = CPSW_MDIO_BASE,
750 .cpsw_base = CPSW_BASE,
753 .cpdma_reg_ofs = 0x800,
755 .slave_data = cpsw_slaves,
756 .ale_reg_ofs = 0xd00,
758 .host_port_reg_ofs = 0x108,
759 .hw_stats_reg_ofs = 0x900,
760 .bd_ram_ofs = 0x2000,
761 .mac_control = (1 << 5),
762 .control = cpsw_control,
764 .version = CPSW_CTRL_VERSION_2,
767 static u64 mac_to_u64(u8 mac[6])
772 for (i = 0; i < 6; i++) {
780 static void u64_to_mac(u64 addr, u8 mac[6])
790 int board_eth_init(bd_t *bis)
794 uint32_t mac_hi, mac_lo;
798 u8 mac_addr1[6], mac_addr2[6];
801 /* try reading mac address from efuse */
802 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
803 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
804 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
805 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
806 mac_addr[2] = mac_hi & 0xFF;
807 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
808 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
809 mac_addr[5] = mac_lo & 0xFF;
811 if (!getenv("ethaddr")) {
812 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
814 if (is_valid_ethaddr(mac_addr))
815 eth_setenv_enetaddr("ethaddr", mac_addr);
818 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
819 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
820 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
821 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
822 mac_addr[2] = mac_hi & 0xFF;
823 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
824 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
825 mac_addr[5] = mac_lo & 0xFF;
827 if (!getenv("eth1addr")) {
828 if (is_valid_ethaddr(mac_addr))
829 eth_setenv_enetaddr("eth1addr", mac_addr);
832 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
834 writel(ctrl_val, (*ctrl)->control_core_control_io1);
836 /* The phy address for the AM57xx IDK are different than x15 */
837 if (board_is_am572x_idk() || board_is_am571x_idk()) {
838 cpsw_data.slave_data[0].phy_addr = 0;
839 cpsw_data.slave_data[1].phy_addr = 1;
842 ret = cpsw_register(&cpsw_data);
844 printf("Error %d registering CPSW switch\n", ret);
847 * Export any Ethernet MAC addresses from EEPROM.
848 * On AM57xx the 2 MAC addresses define the address range
850 board_ti_get_eth_mac_addr(0, mac_addr1);
851 board_ti_get_eth_mac_addr(1, mac_addr2);
853 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
854 mac1 = mac_to_u64(mac_addr1);
855 mac2 = mac_to_u64(mac_addr2);
857 /* must contain an address range */
858 num_macs = mac2 - mac1 + 1;
859 /* <= 50 to protect against user programming error */
860 if (num_macs > 0 && num_macs <= 50) {
861 for (i = 0; i < num_macs; i++) {
862 u64_to_mac(mac1 + i, mac_addr);
863 if (is_valid_ethaddr(mac_addr)) {
864 eth_setenv_enetaddr_by_index("eth",
876 #ifdef CONFIG_BOARD_EARLY_INIT_F
877 /* VTT regulator enable */
878 static inline void vtt_regulator_enable(void)
880 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
883 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
884 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
887 int board_early_init_f(void)
889 vtt_regulator_enable();
894 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
895 int ft_board_setup(void *blob, bd_t *bd)
897 ft_cpu_setup(blob, bd);
903 #ifdef CONFIG_SPL_LOAD_FIT
904 int board_fit_config_name_match(const char *name)
906 if (board_is_x15()) {
907 if (board_is_x15_revb1()) {
908 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
910 } else if (!strcmp(name, "am57xx-beagle-x15")) {
913 } else if (board_is_am572x_evm() &&
914 !strcmp(name, "am57xx-beagle-x15")) {
916 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
918 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
926 #ifdef CONFIG_TI_SECURE_DEVICE
927 void board_fit_image_post_process(void **p_image, size_t *p_size)
929 secure_boot_verify_image(p_image, p_size);
932 void board_tee_image_process(ulong tee_image, size_t tee_size)
934 secure_tee_install((u32)tee_image);
937 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);