2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/omap.h>
26 #include <environment.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
33 #include "../common/board_detect.h"
36 #define board_is_x15() board_ti_is("BBRDX15_")
37 #define board_is_am572x_evm() board_ti_is("AM572PM_")
38 #define board_is_am572x_idk() board_ti_is("AM572IDK")
40 #ifdef CONFIG_DRIVER_TI_CPSW
44 DECLARE_GLOBAL_DATA_PTR;
47 #define GPIO_DDR_VTT_EN 203
49 #define SYSINFO_BOARD_NAME_MAX_LEN 45
51 const struct omap_sysinfo sysinfo = {
52 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
55 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
56 .dmm_lisa_map_3 = 0x80740300,
60 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
62 *dmm_lisa_regs = &beagle_x15_lisa_regs;
65 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
66 .sdram_config_init = 0x61851b32,
67 .sdram_config = 0x61851b32,
68 .sdram_config2 = 0x08000000,
69 .ref_ctrl = 0x000040F1,
70 .ref_ctrl_final = 0x00001035,
71 .sdram_tim1 = 0xcccf36ab,
72 .sdram_tim2 = 0x308f7fda,
73 .sdram_tim3 = 0x409f88a8,
74 .read_idle_ctrl = 0x00050000,
75 .zq_config = 0x5007190b,
76 .temp_alert_config = 0x00000000,
77 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
78 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
79 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
80 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
81 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
82 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
83 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
84 .emif_rd_wr_lvl_rmp_win = 0x00000000,
85 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
86 .emif_rd_wr_lvl_ctl = 0x00000000,
87 .emif_rd_wr_exec_thresh = 0x00000305
90 /* Ext phy ctrl regs 1-35 */
91 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
129 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
130 .sdram_config_init = 0x61851b32,
131 .sdram_config = 0x61851b32,
132 .sdram_config2 = 0x08000000,
133 .ref_ctrl = 0x000040F1,
134 .ref_ctrl_final = 0x00001035,
135 .sdram_tim1 = 0xcccf36b3,
136 .sdram_tim2 = 0x308f7fda,
137 .sdram_tim3 = 0x407f88a8,
138 .read_idle_ctrl = 0x00050000,
139 .zq_config = 0x5007190b,
140 .temp_alert_config = 0x00000000,
141 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
142 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
143 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
144 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
145 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
146 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
147 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
148 .emif_rd_wr_lvl_rmp_win = 0x00000000,
149 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
150 .emif_rd_wr_lvl_ctl = 0x00000000,
151 .emif_rd_wr_exec_thresh = 0x00000305
154 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
192 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
196 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
199 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
204 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
208 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
209 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
212 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
213 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
218 struct vcores_data beagle_x15_volts = {
219 .mpu.value = VDD_MPU_DRA752,
220 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
221 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
222 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
223 .mpu.pmic = &tps659038,
224 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
226 .eve.value = VDD_EVE_DRA752,
227 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
228 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
229 .eve.addr = TPS659038_REG_ADDR_SMPS45,
230 .eve.pmic = &tps659038,
232 .gpu.value = VDD_GPU_DRA752,
233 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
234 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
235 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
236 .gpu.pmic = &tps659038,
238 .core.value = VDD_CORE_DRA752,
239 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
240 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
241 .core.addr = TPS659038_REG_ADDR_SMPS6,
242 .core.pmic = &tps659038,
244 .iva.value = VDD_IVA_DRA752,
245 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
246 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
247 .iva.addr = TPS659038_REG_ADDR_SMPS45,
248 .iva.pmic = &tps659038,
251 #ifdef CONFIG_SPL_BUILD
252 /* No env to setup for SPL */
253 static inline void setup_board_eeprom_env(void) { }
255 /* Override function to read eeprom information */
256 void do_board_detect(void)
260 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
261 CONFIG_EEPROM_CHIP_ADDRESS);
263 printf("ti_i2c_eeprom_init failed %d\n", rc);
266 #else /* CONFIG_SPL_BUILD */
268 /* Override function to read eeprom information: actual i2c read done by SPL*/
269 void do_board_detect(void)
274 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
275 CONFIG_EEPROM_CHIP_ADDRESS);
277 printf("ti_i2c_eeprom_init failed %d\n", rc);
280 bname = "BeagleBoard X15";
281 else if (board_is_am572x_evm())
282 bname = "AM572x EVM";
283 else if (board_is_am572x_idk())
284 bname = "AM572x IDK";
287 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
288 "Board: %s REV %s\n", bname, board_ti_get_rev());
291 static void setup_board_eeprom_env(void)
293 char *name = "beagle_x15";
296 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
297 CONFIG_EEPROM_CHIP_ADDRESS);
301 if (board_is_am572x_evm())
303 else if (board_is_am572x_idk())
306 printf("Unidentified board claims %s in eeprom header\n",
307 board_ti_get_name());
310 set_board_info_env(name);
313 #endif /* CONFIG_SPL_BUILD */
315 void hw_data_init(void)
317 *prcm = &dra7xx_prcm;
318 *dplls_data = &dra7xx_dplls;
319 *omap_vcores = &beagle_x15_volts;
320 *ctrl = &dra7xx_ctrl;
326 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
331 int board_late_init(void)
333 setup_board_eeprom_env();
336 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
337 * This is the POWERHOLD-in-Low behavior.
339 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
343 void set_muxconf_regs(void)
345 do_set_mux32((*ctrl)->control_padconf_core_base,
346 early_padconf, ARRAY_SIZE(early_padconf));
349 #ifdef CONFIG_IODELAY_RECALIBRATION
350 void recalibrate_iodelay(void)
352 const struct pad_conf_entry *pconf;
353 const struct iodelay_cfg_entry *iod;
354 int pconf_sz, iod_sz;
356 if (board_is_am572x_idk()) {
357 pconf = core_padconf_array_essential_am572x_idk;
358 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
359 iod = iodelay_cfg_array_am572x_idk;
360 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
362 /* Common for X15/GPEVM */
363 pconf = core_padconf_array_essential_x15;
364 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
365 iod = iodelay_cfg_array_x15;
366 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
369 __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
373 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
374 int board_mmc_init(bd_t *bis)
376 omap_mmc_init(0, 0, 0, -1, -1);
377 omap_mmc_init(1, 0, 0, -1, -1);
382 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
383 int spl_start_uboot(void)
385 /* break into full u-boot on 'c' */
386 if (serial_tstc() && serial_getc() == 'c')
389 #ifdef CONFIG_SPL_ENV_SUPPORT
392 if (getenv_yesno("boot_os") != 1)
400 #ifdef CONFIG_USB_DWC3
401 static struct dwc3_device usb_otg_ss1 = {
402 .maximum_speed = USB_SPEED_SUPER,
403 .base = DRA7_USB_OTG_SS1_BASE,
404 .tx_fifo_resize = false,
408 static struct dwc3_omap_device usb_otg_ss1_glue = {
409 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
410 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
414 static struct ti_usb_phy_device usb_phy1_device = {
415 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
416 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
417 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
421 static struct dwc3_device usb_otg_ss2 = {
422 .maximum_speed = USB_SPEED_HIGH,
423 .base = DRA7_USB_OTG_SS2_BASE,
424 .tx_fifo_resize = false,
428 static struct dwc3_omap_device usb_otg_ss2_glue = {
429 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
430 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
434 static struct ti_usb_phy_device usb_phy2_device = {
435 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
439 int board_usb_init(int index, enum usb_init_type init)
441 enable_usb_clocks(index);
444 if (init == USB_INIT_DEVICE) {
445 printf("port %d can't be used as device\n", index);
446 disable_usb_clocks(index);
449 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
450 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
451 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
452 OTG_SS_CLKCTRL_MODULEMODE_HW |
453 OPTFCLKEN_REFCLK960M);
456 ti_usb_phy_uboot_init(&usb_phy1_device);
457 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
458 dwc3_uboot_init(&usb_otg_ss1);
461 if (init == USB_INIT_DEVICE) {
462 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
463 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
465 printf("port %d can't be used as host\n", index);
466 disable_usb_clocks(index);
470 ti_usb_phy_uboot_init(&usb_phy2_device);
471 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
472 dwc3_uboot_init(&usb_otg_ss2);
475 printf("Invalid Controller Index\n");
481 int board_usb_cleanup(int index, enum usb_init_type init)
486 ti_usb_phy_uboot_exit(index);
487 dwc3_uboot_exit(index);
488 dwc3_omap_uboot_exit(index);
491 printf("Invalid Controller Index\n");
493 disable_usb_clocks(index);
497 int usb_gadget_handle_interrupts(int index)
501 status = dwc3_omap_uboot_interrupt_status(index);
503 dwc3_uboot_handle_interrupt(index);
509 #ifdef CONFIG_DRIVER_TI_CPSW
511 /* Delay value to add to calibrated value */
512 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
513 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
514 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
515 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
516 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
517 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
518 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
519 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
520 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
521 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
523 static void cpsw_control(int enabled)
525 /* VTP can be added here */
528 static struct cpsw_slave_data cpsw_slaves[] = {
530 .slave_reg_ofs = 0x208,
531 .sliver_reg_ofs = 0xd80,
535 .slave_reg_ofs = 0x308,
536 .sliver_reg_ofs = 0xdc0,
541 static struct cpsw_platform_data cpsw_data = {
542 .mdio_base = CPSW_MDIO_BASE,
543 .cpsw_base = CPSW_BASE,
546 .cpdma_reg_ofs = 0x800,
548 .slave_data = cpsw_slaves,
549 .ale_reg_ofs = 0xd00,
551 .host_port_reg_ofs = 0x108,
552 .hw_stats_reg_ofs = 0x900,
553 .bd_ram_ofs = 0x2000,
554 .mac_control = (1 << 5),
555 .control = cpsw_control,
557 .version = CPSW_CTRL_VERSION_2,
560 static u64 mac_to_u64(u8 mac[6])
565 for (i = 0; i < 6; i++) {
573 static void u64_to_mac(u64 addr, u8 mac[6])
583 int board_eth_init(bd_t *bis)
587 uint32_t mac_hi, mac_lo;
591 u8 mac_addr1[6], mac_addr2[6];
594 /* try reading mac address from efuse */
595 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
596 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
597 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
598 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
599 mac_addr[2] = mac_hi & 0xFF;
600 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
601 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
602 mac_addr[5] = mac_lo & 0xFF;
604 if (!getenv("ethaddr")) {
605 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
607 if (is_valid_ethaddr(mac_addr))
608 eth_setenv_enetaddr("ethaddr", mac_addr);
611 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
612 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
613 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
614 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
615 mac_addr[2] = mac_hi & 0xFF;
616 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
617 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
618 mac_addr[5] = mac_lo & 0xFF;
620 if (!getenv("eth1addr")) {
621 if (is_valid_ethaddr(mac_addr))
622 eth_setenv_enetaddr("eth1addr", mac_addr);
625 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
627 writel(ctrl_val, (*ctrl)->control_core_control_io1);
629 /* The phy address for the AM572x IDK are different than x15 */
630 if (board_is_am572x_idk()) {
631 cpsw_data.slave_data[0].phy_addr = 0;
632 cpsw_data.slave_data[1].phy_addr = 1;
635 ret = cpsw_register(&cpsw_data);
637 printf("Error %d registering CPSW switch\n", ret);
640 * Export any Ethernet MAC addresses from EEPROM.
641 * On AM57xx the 2 MAC addresses define the address range
643 board_ti_get_eth_mac_addr(0, mac_addr1);
644 board_ti_get_eth_mac_addr(1, mac_addr2);
646 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
647 mac1 = mac_to_u64(mac_addr1);
648 mac2 = mac_to_u64(mac_addr2);
650 /* must contain an address range */
651 num_macs = mac2 - mac1 + 1;
652 /* <= 50 to protect against user programming error */
653 if (num_macs > 0 && num_macs <= 50) {
654 for (i = 0; i < num_macs; i++) {
655 u64_to_mac(mac1 + i, mac_addr);
656 if (is_valid_ethaddr(mac_addr)) {
657 eth_setenv_enetaddr_by_index("eth",
669 #ifdef CONFIG_BOARD_EARLY_INIT_F
670 /* VTT regulator enable */
671 static inline void vtt_regulator_enable(void)
673 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
676 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
677 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
680 int board_early_init_f(void)
682 vtt_regulator_enable();