git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  !strncmp("B.10", board_ti_get_rev(), 3))
  40 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  41                                  !strncmp("C.00", board_ti_get_rev(), 3))
  42 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  43 #define board_is_am572x_evm_reva3()     \
  44                                 (board_ti_is("AM572PM_") && \
  45                                  !strncmp("A.30", board_ti_get_rev(), 3))
  46 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  47 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  48 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  49
  50 #ifdef CONFIG_DRIVER_TI_CPSW
  51 #include <cpsw.h>
  52 #endif
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  57 /* GPIO 7_11 */
  58 #define GPIO_DDR_VTT_EN 203
  59
  60 /* Touch screen controller to identify the LCD */
  61 #define OSD_TS_FT_BUS_ADDRESS   0
  62 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  63 #define OSD_TS_FT_REG_ID        0xA3
  64 /*
  65  * Touchscreen IDs for various OSD panels
  66  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  67  */
  68 /* Used on newer osd101t2587 Panels */
  69 #define OSD_TS_FT_ID_5x46       0x54
  70 /* Used on older osd101t2045 Panels */
  71 #define OSD_TS_FT_ID_5606       0x08
  72
  73 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  74
  75 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  76 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  77
  78 const struct omap_sysinfo sysinfo = {
  79         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  80 };
  81
  82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  83         .dmm_lisa_map_3 = 0x80740300,
  84         .is_ma_present  = 0x1
  85 };
  86
  87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  88         .dmm_lisa_map_3 = 0x80640100,
  89         .is_ma_present  = 0x1
  90 };
  91
  92 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  93 {
  94         if (board_is_am571x_idk())
  95                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  96         else
  97                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  98 }
  99
 100 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 101         .sdram_config_init              = 0x61851b32,
 102         .sdram_config                   = 0x61851b32,
 103         .sdram_config2                  = 0x08000000,
 104         .ref_ctrl                       = 0x000040F1,
 105         .ref_ctrl_final                 = 0x00001035,
 106         .sdram_tim1                     = 0xcccf36ab,
 107         .sdram_tim2                     = 0x308f7fda,
 108         .sdram_tim3                     = 0x409f88a8,
 109         .read_idle_ctrl                 = 0x00050000,
 110         .zq_config                      = 0x5007190b,
 111         .temp_alert_config              = 0x00000000,
 112         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 113         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 114         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 115         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 116         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 117         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 118         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 119         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 120         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 121         .emif_rd_wr_lvl_ctl             = 0x00000000,
 122         .emif_rd_wr_exec_thresh         = 0x00000305
 123 };
 124
 125 /* Ext phy ctrl regs 1-35 */
 126 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 127         0x10040100,
 128         0x00910091,
 129         0x00950095,
 130         0x009B009B,
 131         0x009E009E,
 132         0x00980098,
 133         0x00340034,
 134         0x00350035,
 135         0x00340034,
 136         0x00310031,
 137         0x00340034,
 138         0x007F007F,
 139         0x007F007F,
 140         0x007F007F,
 141         0x007F007F,
 142         0x007F007F,
 143         0x00480048,
 144         0x004A004A,
 145         0x00520052,
 146         0x00550055,
 147         0x00500050,
 148         0x00000000,
 149         0x00600020,
 150         0x40011080,
 151         0x08102040,
 152         0x0,
 153         0x0,
 154         0x0,
 155         0x0,
 156         0x0,
 157         0x0,
 158         0x0,
 159         0x0,
 160         0x0,
 161         0x0
 162 };
 163
 164 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 165         .sdram_config_init              = 0x61851b32,
 166         .sdram_config                   = 0x61851b32,
 167         .sdram_config2                  = 0x08000000,
 168         .ref_ctrl                       = 0x000040F1,
 169         .ref_ctrl_final                 = 0x00001035,
 170         .sdram_tim1                     = 0xcccf36b3,
 171         .sdram_tim2                     = 0x308f7fda,
 172         .sdram_tim3                     = 0x407f88a8,
 173         .read_idle_ctrl                 = 0x00050000,
 174         .zq_config                      = 0x5007190b,
 175         .temp_alert_config              = 0x00000000,
 176         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 177         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 178         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 179         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 180         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 181         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 182         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 183         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 184         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 185         .emif_rd_wr_lvl_ctl             = 0x00000000,
 186         .emif_rd_wr_exec_thresh         = 0x00000305
 187 };
 188
 189 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 190         0x10040100,
 191         0x00910091,
 192         0x00950095,
 193         0x009B009B,
 194         0x009E009E,
 195         0x00980098,
 196         0x00340034,
 197         0x00350035,
 198         0x00340034,
 199         0x00310031,
 200         0x00340034,
 201         0x007F007F,
 202         0x007F007F,
 203         0x007F007F,
 204         0x007F007F,
 205         0x007F007F,
 206         0x00480048,
 207         0x004A004A,
 208         0x00520052,
 209         0x00550055,
 210         0x00500050,
 211         0x00000000,
 212         0x00600020,
 213         0x40011080,
 214         0x08102040,
 215         0x0,
 216         0x0,
 217         0x0,
 218         0x0,
 219         0x0,
 220         0x0,
 221         0x0,
 222         0x0,
 223         0x0,
 224         0x0
 225 };
 226
 227 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 228         .sdram_config_init              = 0x61863332,
 229         .sdram_config                   = 0x61863332,
 230         .sdram_config2                  = 0x08000000,
 231         .ref_ctrl                       = 0x0000514d,
 232         .ref_ctrl_final                 = 0x0000144a,
 233         .sdram_tim1                     = 0xd333887c,
 234         .sdram_tim2                     = 0x40b37fe3,
 235         .sdram_tim3                     = 0x409f8ada,
 236         .read_idle_ctrl                 = 0x00050000,
 237         .zq_config                      = 0x5007190b,
 238         .temp_alert_config              = 0x00000000,
 239         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 240         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 241         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 242         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 243         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 244         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 245         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 246         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 247         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 248         .emif_rd_wr_lvl_ctl             = 0x00000000,
 249         .emif_rd_wr_exec_thresh         = 0x00000305
 250 };
 251
 252 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 253 {
 254         switch (emif_nr) {
 255         case 1:
 256                 if (board_is_am571x_idk())
 257                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 258                 else
 259                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 260                 break;
 261         case 2:
 262                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 263                 break;
 264         }
 265 }
 266
 267 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 268 {
 269         switch (emif_nr) {
 270         case 1:
 271                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 272                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 273                 break;
 274         case 2:
 275                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 276                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 277                 break;
 278         }
 279 }
 280
 281 struct vcores_data beagle_x15_volts = {
 282         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 283         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 284         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 285         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 286         .mpu.pmic               = &tps659038,
 287         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 288
 289         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 290         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 291         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 292         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 293         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 294         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 295         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 296         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 297         .eve.pmic               = &tps659038,
 298         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 299
 300         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 301         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 302         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 303         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 304         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 305         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 306         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 307         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 308         .gpu.pmic               = &tps659038,
 309         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 310
 311         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 312         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 313         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 314         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 315         .core.pmic              = &tps659038,
 316
 317         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 318         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 319         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 320         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 321         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 322         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 323         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 324         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 325         .iva.pmic               = &tps659038,
 326         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 327 };
 328
 329 struct vcores_data am572x_idk_volts = {
 330         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 331         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 332         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 333         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 334         .mpu.pmic               = &tps659038,
 335         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 336
 337         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 338         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 339         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 340         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 341         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 342         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 343         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 344         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 345         .eve.pmic               = &tps659038,
 346         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 347
 348         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 349         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 350         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 351         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 352         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 353         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 354         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 355         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 356         .gpu.pmic               = &tps659038,
 357         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 358
 359         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 360         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 361         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 362         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 363         .core.pmic              = &tps659038,
 364
 365         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 366         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 367         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 368         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 369         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 370         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 371         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 372         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 373         .iva.pmic               = &tps659038,
 374         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 375 };
 376
 377 struct vcores_data am571x_idk_volts = {
 378         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 379         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 380         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 381         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 382         .mpu.pmic               = &tps659038,
 383         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 384
 385         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 386         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 387         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 388         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 389         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 390         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 391         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 392         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 393         .eve.pmic               = &tps659038,
 394         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 395
 396         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 397         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 398         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 399         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 400         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 401         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 402         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 403         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 404         .gpu.pmic               = &tps659038,
 405         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 406
 407         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 408         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 409         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 410         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 411         .core.pmic              = &tps659038,
 412
 413         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 414         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 415         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 416         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 417         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 418         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 419         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 420         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 421         .iva.pmic               = &tps659038,
 422         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 423 };
 424
 425 int get_voltrail_opp(int rail_offset)
 426 {
 427         int opp;
 428
 429         switch (rail_offset) {
 430         case VOLT_MPU:
 431                 opp = DRA7_MPU_OPP;
 432                 break;
 433         case VOLT_CORE:
 434                 opp = DRA7_CORE_OPP;
 435                 break;
 436         case VOLT_GPU:
 437                 opp = DRA7_GPU_OPP;
 438                 break;
 439         case VOLT_EVE:
 440                 opp = DRA7_DSPEVE_OPP;
 441                 break;
 442         case VOLT_IVA:
 443                 opp = DRA7_IVA_OPP;
 444                 break;
 445         default:
 446                 opp = OPP_NOM;
 447         }
 448
 449         return opp;
 450 }
 451
 452
 453 #ifdef CONFIG_SPL_BUILD
 454 /* No env to setup for SPL */
 455 static inline void setup_board_eeprom_env(void) { }
 456
 457 /* Override function to read eeprom information */
 458 void do_board_detect(void)
 459 {
 460         int rc;
 461
 462         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 463                                   CONFIG_EEPROM_CHIP_ADDRESS);
 464         if (rc)
 465                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 466 }
 467
 468 #else   /* CONFIG_SPL_BUILD */
 469
 470 /* Override function to read eeprom information: actual i2c read done by SPL*/
 471 void do_board_detect(void)
 472 {
 473         char *bname = NULL;
 474         int rc;
 475
 476         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 477                                   CONFIG_EEPROM_CHIP_ADDRESS);
 478         if (rc)
 479                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 480
 481         if (board_is_x15())
 482                 bname = "BeagleBoard X15";
 483         else if (board_is_am572x_evm())
 484                 bname = "AM572x EVM";
 485         else if (board_is_am574x_idk())
 486                 bname = "AM574x IDK";
 487         else if (board_is_am572x_idk())
 488                 bname = "AM572x IDK";
 489         else if (board_is_am571x_idk())
 490                 bname = "AM571x IDK";
 491
 492         if (bname)
 493                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 494                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 495 }
 496
 497 static void setup_board_eeprom_env(void)
 498 {
 499         char *name = "beagle_x15";
 500         int rc;
 501
 502         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 503                                   CONFIG_EEPROM_CHIP_ADDRESS);
 504         if (rc)
 505                 goto invalid_eeprom;
 506
 507         if (board_is_x15()) {
 508                 if (board_is_x15_revb1())
 509                         name = "beagle_x15_revb1";
 510                 else if (board_is_x15_revc())
 511                         name = "beagle_x15_revc";
 512                 else
 513                         name = "beagle_x15";
 514         } else if (board_is_am572x_evm()) {
 515                 if (board_is_am572x_evm_reva3())
 516                         name = "am57xx_evm_reva3";
 517                 else
 518                         name = "am57xx_evm";
 519         } else if (board_is_am574x_idk()) {
 520                 name = "am574x_idk";
 521         } else if (board_is_am572x_idk()) {
 522                 name = "am572x_idk";
 523         } else if (board_is_am571x_idk()) {
 524                 name = "am571x_idk";
 525         } else {
 526                 printf("Unidentified board claims %s in eeprom header\n",
 527                        board_ti_get_name());
 528         }
 529
 530 invalid_eeprom:
 531         set_board_info_env(name);
 532 }
 533
 534 #endif  /* CONFIG_SPL_BUILD */
 535
 536 void vcores_init(void)
 537 {
 538         if (board_is_am572x_idk() || board_is_am574x_idk())
 539                 *omap_vcores = &am572x_idk_volts;
 540         else if (board_is_am571x_idk())
 541                 *omap_vcores = &am571x_idk_volts;
 542         else
 543                 *omap_vcores = &beagle_x15_volts;
 544 }
 545
 546 void hw_data_init(void)
 547 {
 548         *prcm = &dra7xx_prcm;
 549         if (is_dra72x())
 550                 *dplls_data = &dra72x_dplls;
 551         else if (is_dra76x())
 552                 *dplls_data = &dra76x_dplls;
 553         else
 554                 *dplls_data = &dra7xx_dplls;
 555         *ctrl = &dra7xx_ctrl;
 556 }
 557
 558 bool am571x_idk_needs_lcd(void)
 559 {
 560         bool needs_lcd;
 561
 562         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 563         if (gpio_get_value(GPIO_ETH_LCD))
 564                 needs_lcd = false;
 565         else
 566                 needs_lcd = true;
 567
 568         gpio_free(GPIO_ETH_LCD);
 569
 570         return needs_lcd;
 571 }
 572
 573 int board_init(void)
 574 {
 575         gpmc_init();
 576         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 577
 578         return 0;
 579 }
 580
 581 void am57x_idk_lcd_detect(void)
 582 {
 583         int r = -ENODEV;
 584         char *idk_lcd = "no";
 585         uint8_t buf = 0;
 586
 587         /* Only valid for IDKs */
 588         if (board_is_x15() || board_is_am572x_evm())
 589                 return;
 590
 591         /* Only AM571x IDK has gpio control detect.. so check that */
 592         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 593                 goto out;
 594
 595         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 596         if (r) {
 597                 printf("%s: Failed to set bus address to %d: %d\n",
 598                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 599                 goto out;
 600         }
 601         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 602         if (r) {
 603                 /* AM572x IDK has no explicit settings for optional LCD kit */
 604                 if (board_is_am571x_idk()) {
 605                         printf("%s: Touch screen detect failed: %d!\n",
 606                                __func__, r);
 607                 }
 608                 goto out;
 609         }
 610
 611         /* Read FT ID */
 612         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 613         if (r) {
 614                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 615                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 616                        OSD_TS_FT_REG_ID, r);
 617                 goto out;
 618         }
 619
 620         switch (buf) {
 621         case OSD_TS_FT_ID_5606:
 622                 idk_lcd = "osd101t2045";
 623                 break;
 624         case OSD_TS_FT_ID_5x46:
 625                 idk_lcd = "osd101t2587";
 626                 break;
 627         default:
 628                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 629                        __func__, buf);
 630                 /* we will let default be "no lcd" */
 631         }
 632 out:
 633         env_set("idk_lcd", idk_lcd);
 634         return;
 635 }
 636
 637 int board_late_init(void)
 638 {
 639         setup_board_eeprom_env();
 640         u8 val;
 641
 642         /*
 643          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 644          * This is the POWERHOLD-in-Low behavior.
 645          */
 646         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 647
 648         /*
 649          * Default FIT boot on HS devices. Non FIT images are not allowed
 650          * on HS devices.
 651          */
 652         if (get_device_type() == HS_DEVICE)
 653                 env_set("boot_fit", "1");
 654
 655         /*
 656          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 657          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 658          * PMIC Power off. So to be on the safer side set it back
 659          * to POWERHOLD mode irrespective of the current state.
 660          */
 661         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 662                            &val);
 663         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 664         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 665                             val);
 666
 667         omap_die_id_serial();
 668         omap_set_fastboot_vars();
 669
 670         am57x_idk_lcd_detect();
 671
 672 #if !defined(CONFIG_SPL_BUILD)
 673         board_ti_set_ethaddr(2);
 674 #endif
 675
 676         return 0;
 677 }
 678
 679 void set_muxconf_regs(void)
 680 {
 681         do_set_mux32((*ctrl)->control_padconf_core_base,
 682                      early_padconf, ARRAY_SIZE(early_padconf));
 683 }
 684
 685 #ifdef CONFIG_IODELAY_RECALIBRATION
 686 void recalibrate_iodelay(void)
 687 {
 688         const struct pad_conf_entry *pconf;
 689         const struct iodelay_cfg_entry *iod, *delta_iod;
 690         int pconf_sz, iod_sz, delta_iod_sz = 0;
 691         int ret;
 692
 693         if (board_is_am572x_idk() || board_is_am574x_idk()) {
 694                 pconf = core_padconf_array_essential_am572x_idk;
 695                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 696                 iod = iodelay_cfg_array_am572x_idk;
 697                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 698         } else if (board_is_am571x_idk()) {
 699                 pconf = core_padconf_array_essential_am571x_idk;
 700                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 701                 iod = iodelay_cfg_array_am571x_idk;
 702                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 703         } else {
 704                 /* Common for X15/GPEVM */
 705                 pconf = core_padconf_array_essential_x15;
 706                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 707                 /* There never was an SR1.0 X15.. So.. */
 708                 if (omap_revision() == DRA752_ES1_1) {
 709                         iod = iodelay_cfg_array_x15_sr1_1;
 710                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 711                 } else {
 712                         /* Since full production should switch to SR2.0  */
 713                         iod = iodelay_cfg_array_x15_sr2_0;
 714                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 715                 }
 716         }
 717
 718         /* Setup I/O isolation */
 719         ret = __recalibrate_iodelay_start();
 720         if (ret)
 721                 goto err;
 722
 723         /* Do the muxing here */
 724         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 725
 726         /* Now do the weird minor deltas that should be safe */
 727         if (board_is_x15() || board_is_am572x_evm()) {
 728                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 729                     board_is_x15_revc()) {
 730                         pconf = core_padconf_array_delta_x15_sr2_0;
 731                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 732                 } else {
 733                         pconf = core_padconf_array_delta_x15_sr1_1;
 734                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 735                 }
 736                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 737         }
 738
 739         if (board_is_am571x_idk()) {
 740                 if (am571x_idk_needs_lcd()) {
 741                         pconf = core_padconf_array_vout_am571x_idk;
 742                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 743                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 744                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 745
 746                 } else {
 747                         pconf = core_padconf_array_icss1eth_am571x_idk;
 748                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 749                 }
 750                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 751         }
 752
 753         /* Setup IOdelay configuration */
 754         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 755         if (delta_iod_sz)
 756                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 757                                      delta_iod_sz);
 758
 759 err:
 760         /* Closeup.. remove isolation */
 761         __recalibrate_iodelay_end(ret);
 762 }
 763 #endif
 764
 765 #if defined(CONFIG_MMC)
 766 int board_mmc_init(bd_t *bis)
 767 {
 768         omap_mmc_init(0, 0, 0, -1, -1);
 769         omap_mmc_init(1, 0, 0, -1, -1);
 770         return 0;
 771 }
 772 #endif
 773
 774 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 775 int spl_start_uboot(void)
 776 {
 777         /* break into full u-boot on 'c' */
 778         if (serial_tstc() && serial_getc() == 'c')
 779                 return 1;
 780
 781 #ifdef CONFIG_SPL_ENV_SUPPORT
 782         env_init();
 783         env_load();
 784         if (env_get_yesno("boot_os") != 1)
 785                 return 1;
 786 #endif
 787
 788         return 0;
 789 }
 790 #endif
 791
 792 #ifdef CONFIG_USB_DWC3
 793 static struct dwc3_device usb_otg_ss2 = {
 794         .maximum_speed = USB_SPEED_HIGH,
 795         .base = DRA7_USB_OTG_SS2_BASE,
 796         .tx_fifo_resize = false,
 797         .index = 1,
 798 };
 799
 800 static struct dwc3_omap_device usb_otg_ss2_glue = {
 801         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 802         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 803         .index = 1,
 804 };
 805
 806 static struct ti_usb_phy_device usb_phy2_device = {
 807         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 808         .index = 1,
 809 };
 810
 811 int usb_gadget_handle_interrupts(int index)
 812 {
 813         u32 status;
 814
 815         status = dwc3_omap_uboot_interrupt_status(index);
 816         if (status)
 817                 dwc3_uboot_handle_interrupt(index);
 818
 819         return 0;
 820 }
 821 #endif /* CONFIG_USB_DWC3 */
 822
 823 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 824 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 825 {
 826         enable_usb_clocks(index);
 827         switch (index) {
 828         case 0:
 829                 if (init == USB_INIT_DEVICE) {
 830                         printf("port %d can't be used as device\n", index);
 831                         disable_usb_clocks(index);
 832                         return -EINVAL;
 833                 }
 834                 break;
 835         case 1:
 836                 if (init == USB_INIT_DEVICE) {
 837 #ifdef CONFIG_USB_DWC3
 838                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 839                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 840                         ti_usb_phy_uboot_init(&usb_phy2_device);
 841                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 842                         dwc3_uboot_init(&usb_otg_ss2);
 843 #endif
 844                 } else {
 845                         printf("port %d can't be used as host\n", index);
 846                         disable_usb_clocks(index);
 847                         return -EINVAL;
 848                 }
 849
 850                 break;
 851         default:
 852                 printf("Invalid Controller Index\n");
 853         }
 854
 855         return 0;
 856 }
 857
 858 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 859 {
 860 #ifdef CONFIG_USB_DWC3
 861         switch (index) {
 862         case 0:
 863         case 1:
 864                 if (init == USB_INIT_DEVICE) {
 865                         ti_usb_phy_uboot_exit(index);
 866                         dwc3_uboot_exit(index);
 867                         dwc3_omap_uboot_exit(index);
 868                 }
 869                 break;
 870         default:
 871                 printf("Invalid Controller Index\n");
 872         }
 873 #endif
 874         disable_usb_clocks(index);
 875         return 0;
 876 }
 877 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 878
 879 #ifdef CONFIG_DRIVER_TI_CPSW
 880
 881 /* Delay value to add to calibrated value */
 882 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 883 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 884 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 885 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 886 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 887 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 888 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 889 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 890 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 891 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 892
 893 static void cpsw_control(int enabled)
 894 {
 895         /* VTP can be added here */
 896 }
 897
 898 static struct cpsw_slave_data cpsw_slaves[] = {
 899         {
 900                 .slave_reg_ofs  = 0x208,
 901                 .sliver_reg_ofs = 0xd80,
 902                 .phy_addr       = 1,
 903         },
 904         {
 905                 .slave_reg_ofs  = 0x308,
 906                 .sliver_reg_ofs = 0xdc0,
 907                 .phy_addr       = 2,
 908         },
 909 };
 910
 911 static struct cpsw_platform_data cpsw_data = {
 912         .mdio_base              = CPSW_MDIO_BASE,
 913         .cpsw_base              = CPSW_BASE,
 914         .mdio_div               = 0xff,
 915         .channels               = 8,
 916         .cpdma_reg_ofs          = 0x800,
 917         .slaves                 = 1,
 918         .slave_data             = cpsw_slaves,
 919         .ale_reg_ofs            = 0xd00,
 920         .ale_entries            = 1024,
 921         .host_port_reg_ofs      = 0x108,
 922         .hw_stats_reg_ofs       = 0x900,
 923         .bd_ram_ofs             = 0x2000,
 924         .mac_control            = (1 << 5),
 925         .control                = cpsw_control,
 926         .host_port_num          = 0,
 927         .version                = CPSW_CTRL_VERSION_2,
 928 };
 929
 930 static u64 mac_to_u64(u8 mac[6])
 931 {
 932         int i;
 933         u64 addr = 0;
 934
 935         for (i = 0; i < 6; i++) {
 936                 addr <<= 8;
 937                 addr |= mac[i];
 938         }
 939
 940         return addr;
 941 }
 942
 943 static void u64_to_mac(u64 addr, u8 mac[6])
 944 {
 945         mac[5] = addr;
 946         mac[4] = addr >> 8;
 947         mac[3] = addr >> 16;
 948         mac[2] = addr >> 24;
 949         mac[1] = addr >> 32;
 950         mac[0] = addr >> 40;
 951 }
 952
 953 int board_eth_init(bd_t *bis)
 954 {
 955         int ret;
 956         uint8_t mac_addr[6];
 957         uint32_t mac_hi, mac_lo;
 958         uint32_t ctrl_val;
 959         int i;
 960         u64 mac1, mac2;
 961         u8 mac_addr1[6], mac_addr2[6];
 962         int num_macs;
 963
 964         /* try reading mac address from efuse */
 965         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 966         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 967         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 968         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 969         mac_addr[2] = mac_hi & 0xFF;
 970         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 971         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 972         mac_addr[5] = mac_lo & 0xFF;
 973
 974         if (!env_get("ethaddr")) {
 975                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 976
 977                 if (is_valid_ethaddr(mac_addr))
 978                         eth_env_set_enetaddr("ethaddr", mac_addr);
 979         }
 980
 981         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 982         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 983         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 984         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 985         mac_addr[2] = mac_hi & 0xFF;
 986         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 987         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 988         mac_addr[5] = mac_lo & 0xFF;
 989
 990         if (!env_get("eth1addr")) {
 991                 if (is_valid_ethaddr(mac_addr))
 992                         eth_env_set_enetaddr("eth1addr", mac_addr);
 993         }
 994
 995         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 996         ctrl_val |= 0x22;
 997         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 998
 999         /* The phy address for the AM57xx IDK are different than x15 */
1000         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1001             board_is_am574x_idk()) {
1002                 cpsw_data.slave_data[0].phy_addr = 0;
1003                 cpsw_data.slave_data[1].phy_addr = 1;
1004         }
1005
1006         ret = cpsw_register(&cpsw_data);
1007         if (ret < 0)
1008                 printf("Error %d registering CPSW switch\n", ret);
1009
1010         /*
1011          * Export any Ethernet MAC addresses from EEPROM.
1012          * On AM57xx the 2 MAC addresses define the address range
1013          */
1014         board_ti_get_eth_mac_addr(0, mac_addr1);
1015         board_ti_get_eth_mac_addr(1, mac_addr2);
1016
1017         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1018                 mac1 = mac_to_u64(mac_addr1);
1019                 mac2 = mac_to_u64(mac_addr2);
1020
1021                 /* must contain an address range */
1022                 num_macs = mac2 - mac1 + 1;
1023                 /* <= 50 to protect against user programming error */
1024                 if (num_macs > 0 && num_macs <= 50) {
1025                         for (i = 0; i < num_macs; i++) {
1026                                 u64_to_mac(mac1 + i, mac_addr);
1027                                 if (is_valid_ethaddr(mac_addr)) {
1028                                         eth_env_set_enetaddr_by_index("eth",
1029                                                                       i + 2,
1030                                                                       mac_addr);
1031                                 }
1032                         }
1033                 }
1034         }
1035
1036         return ret;
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_BOARD_EARLY_INIT_F
1041 /* VTT regulator enable */
1042 static inline void vtt_regulator_enable(void)
1043 {
1044         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1045                 return;
1046
1047         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1048         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1049 }
1050
1051 int board_early_init_f(void)
1052 {
1053         vtt_regulator_enable();
1054         return 0;
1055 }
1056 #endif
1057
1058 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1059 int ft_board_setup(void *blob, bd_t *bd)
1060 {
1061         ft_cpu_setup(blob, bd);
1062
1063         return 0;
1064 }
1065 #endif
1066
1067 #ifdef CONFIG_SPL_LOAD_FIT
1068 int board_fit_config_name_match(const char *name)
1069 {
1070         if (board_is_x15()) {
1071                 if (board_is_x15_revb1()) {
1072                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1073                                 return 0;
1074                 } else if (board_is_x15_revc()) {
1075                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1076                                 return 0;
1077                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1078                         return 0;
1079                 }
1080         } else if (board_is_am572x_evm() &&
1081                    !strcmp(name, "am57xx-beagle-x15")) {
1082                 return 0;
1083         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1084                 return 0;
1085         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1086                 return 0;
1087         }
1088
1089         return -1;
1090 }
1091 #endif
1092
1093 #ifdef CONFIG_TI_SECURE_DEVICE
1094 void board_fit_image_post_process(void **p_image, size_t *p_size)
1095 {
1096         secure_boot_verify_image(p_image, p_size);
1097 }
1098
1099 void board_tee_image_process(ulong tee_image, size_t tee_size)
1100 {
1101         secure_tee_install((u32)tee_image);
1102 }
1103
1104 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1105 #endif