2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
40 #define board_is_am572x_evm() board_ti_is("AM572PM_")
41 #define board_is_am572x_evm_reva3() \
42 (board_ti_is("AM572PM_") && \
43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
44 #define board_is_am572x_idk() board_ti_is("AM572IDK")
45 #define board_is_am571x_idk() board_ti_is("AM571IDK")
47 #ifdef CONFIG_DRIVER_TI_CPSW
51 DECLARE_GLOBAL_DATA_PTR;
54 #define GPIO_DDR_VTT_EN 203
56 #define SYSINFO_BOARD_NAME_MAX_LEN 45
58 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
59 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
61 const struct omap_sysinfo sysinfo = {
62 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
65 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
66 .dmm_lisa_map_3 = 0x80740300,
70 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
71 .dmm_lisa_map_3 = 0x80640100,
75 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
77 if (board_is_am571x_idk())
78 *dmm_lisa_regs = &am571x_idk_lisa_regs;
80 *dmm_lisa_regs = &beagle_x15_lisa_regs;
83 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
84 .sdram_config_init = 0x61851b32,
85 .sdram_config = 0x61851b32,
86 .sdram_config2 = 0x08000000,
87 .ref_ctrl = 0x000040F1,
88 .ref_ctrl_final = 0x00001035,
89 .sdram_tim1 = 0xcccf36ab,
90 .sdram_tim2 = 0x308f7fda,
91 .sdram_tim3 = 0x409f88a8,
92 .read_idle_ctrl = 0x00050000,
93 .zq_config = 0x5007190b,
94 .temp_alert_config = 0x00000000,
95 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
96 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
97 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
98 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
99 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
100 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
101 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
102 .emif_rd_wr_lvl_rmp_win = 0x00000000,
103 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
104 .emif_rd_wr_lvl_ctl = 0x00000000,
105 .emif_rd_wr_exec_thresh = 0x00000305
108 /* Ext phy ctrl regs 1-35 */
109 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
147 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
148 .sdram_config_init = 0x61851b32,
149 .sdram_config = 0x61851b32,
150 .sdram_config2 = 0x08000000,
151 .ref_ctrl = 0x000040F1,
152 .ref_ctrl_final = 0x00001035,
153 .sdram_tim1 = 0xcccf36b3,
154 .sdram_tim2 = 0x308f7fda,
155 .sdram_tim3 = 0x407f88a8,
156 .read_idle_ctrl = 0x00050000,
157 .zq_config = 0x5007190b,
158 .temp_alert_config = 0x00000000,
159 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
160 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
161 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
162 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
163 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
164 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
165 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
166 .emif_rd_wr_lvl_rmp_win = 0x00000000,
167 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
168 .emif_rd_wr_lvl_ctl = 0x00000000,
169 .emif_rd_wr_exec_thresh = 0x00000305
172 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
210 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
217 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
222 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
226 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
227 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
230 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
231 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
236 struct vcores_data beagle_x15_volts = {
237 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
238 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
239 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
240 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
241 .mpu.pmic = &tps659038,
242 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
244 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
245 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
246 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
247 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
248 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
249 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
250 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
251 .eve.addr = TPS659038_REG_ADDR_SMPS45,
252 .eve.pmic = &tps659038,
253 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
255 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
256 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
257 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
258 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
259 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
260 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
261 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
262 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
263 .gpu.pmic = &tps659038,
264 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
266 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
267 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
268 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
269 .core.addr = TPS659038_REG_ADDR_SMPS6,
270 .core.pmic = &tps659038,
272 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
273 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
274 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
275 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
276 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
277 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
278 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
279 .iva.addr = TPS659038_REG_ADDR_SMPS45,
280 .iva.pmic = &tps659038,
281 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
284 struct vcores_data am572x_idk_volts = {
285 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
286 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
287 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
288 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
289 .mpu.pmic = &tps659038,
290 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
292 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
293 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
294 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
295 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
296 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
297 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
298 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
299 .eve.addr = TPS659038_REG_ADDR_SMPS45,
300 .eve.pmic = &tps659038,
301 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
303 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
304 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
305 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
306 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
307 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
308 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
309 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
310 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
311 .gpu.pmic = &tps659038,
312 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
314 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
315 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
316 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
317 .core.addr = TPS659038_REG_ADDR_SMPS7,
318 .core.pmic = &tps659038,
320 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
321 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
322 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
323 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
324 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
325 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
326 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
327 .iva.addr = TPS659038_REG_ADDR_SMPS8,
328 .iva.pmic = &tps659038,
329 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
332 int get_voltrail_opp(int rail_offset)
336 switch (rail_offset) {
347 opp = DRA7_DSPEVE_OPP;
360 #ifdef CONFIG_SPL_BUILD
361 /* No env to setup for SPL */
362 static inline void setup_board_eeprom_env(void) { }
364 /* Override function to read eeprom information */
365 void do_board_detect(void)
369 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
370 CONFIG_EEPROM_CHIP_ADDRESS);
372 printf("ti_i2c_eeprom_init failed %d\n", rc);
375 #else /* CONFIG_SPL_BUILD */
377 /* Override function to read eeprom information: actual i2c read done by SPL*/
378 void do_board_detect(void)
383 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
384 CONFIG_EEPROM_CHIP_ADDRESS);
386 printf("ti_i2c_eeprom_init failed %d\n", rc);
389 bname = "BeagleBoard X15";
390 else if (board_is_am572x_evm())
391 bname = "AM572x EVM";
392 else if (board_is_am572x_idk())
393 bname = "AM572x IDK";
394 else if (board_is_am571x_idk())
395 bname = "AM571x IDK";
398 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
399 "Board: %s REV %s\n", bname, board_ti_get_rev());
402 static void setup_board_eeprom_env(void)
404 char *name = "beagle_x15";
407 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
408 CONFIG_EEPROM_CHIP_ADDRESS);
412 if (board_is_x15()) {
413 if (board_is_x15_revb1())
414 name = "beagle_x15_revb1";
417 } else if (board_is_am572x_evm()) {
418 if (board_is_am572x_evm_reva3())
419 name = "am57xx_evm_reva3";
422 } else if (board_is_am572x_idk()) {
424 } else if (board_is_am571x_idk()) {
427 printf("Unidentified board claims %s in eeprom header\n",
428 board_ti_get_name());
432 set_board_info_env(name);
435 #endif /* CONFIG_SPL_BUILD */
437 void vcores_init(void)
439 if (board_is_am572x_idk())
440 *omap_vcores = &am572x_idk_volts;
442 *omap_vcores = &beagle_x15_volts;
445 void hw_data_init(void)
447 *prcm = &dra7xx_prcm;
448 *dplls_data = &dra7xx_dplls;
449 *ctrl = &dra7xx_ctrl;
455 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
460 int board_late_init(void)
462 setup_board_eeprom_env();
466 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
467 * This is the POWERHOLD-in-Low behavior.
469 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
472 * Default FIT boot on HS devices. Non FIT images are not allowed
475 if (get_device_type() == HS_DEVICE)
476 setenv("boot_fit", "1");
479 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
480 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
481 * PMIC Power off. So to be on the safer side set it back
482 * to POWERHOLD mode irrespective of the current state.
484 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
486 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
487 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
493 void set_muxconf_regs(void)
495 do_set_mux32((*ctrl)->control_padconf_core_base,
496 early_padconf, ARRAY_SIZE(early_padconf));
499 #ifdef CONFIG_IODELAY_RECALIBRATION
500 void recalibrate_iodelay(void)
502 const struct pad_conf_entry *pconf;
503 const struct iodelay_cfg_entry *iod;
504 int pconf_sz, iod_sz;
507 if (board_is_am572x_idk()) {
508 pconf = core_padconf_array_essential_am572x_idk;
509 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
510 iod = iodelay_cfg_array_am572x_idk;
511 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
512 } else if (board_is_am571x_idk()) {
513 pconf = core_padconf_array_essential_am571x_idk;
514 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
515 iod = iodelay_cfg_array_am571x_idk;
516 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
518 /* Common for X15/GPEVM */
519 pconf = core_padconf_array_essential_x15;
520 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
521 /* There never was an SR1.0 X15.. So.. */
522 if (omap_revision() == DRA752_ES1_1) {
523 iod = iodelay_cfg_array_x15_sr1_1;
524 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
526 /* Since full production should switch to SR2.0 */
527 iod = iodelay_cfg_array_x15_sr2_0;
528 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
532 /* Setup I/O isolation */
533 ret = __recalibrate_iodelay_start();
537 /* Do the muxing here */
538 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
540 /* Now do the weird minor deltas that should be safe */
541 if (board_is_x15() || board_is_am572x_evm()) {
542 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
543 pconf = core_padconf_array_delta_x15_sr2_0;
544 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
546 pconf = core_padconf_array_delta_x15_sr1_1;
547 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
549 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
552 /* Setup IOdelay configuration */
553 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
555 /* Closeup.. remove isolation */
556 __recalibrate_iodelay_end(ret);
560 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
561 int board_mmc_init(bd_t *bis)
563 omap_mmc_init(0, 0, 0, -1, -1);
564 omap_mmc_init(1, 0, 0, -1, -1);
569 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
570 int spl_start_uboot(void)
572 /* break into full u-boot on 'c' */
573 if (serial_tstc() && serial_getc() == 'c')
576 #ifdef CONFIG_SPL_ENV_SUPPORT
579 if (getenv_yesno("boot_os") != 1)
587 #ifdef CONFIG_USB_DWC3
588 static struct dwc3_device usb_otg_ss2 = {
589 .maximum_speed = USB_SPEED_HIGH,
590 .base = DRA7_USB_OTG_SS2_BASE,
591 .tx_fifo_resize = false,
595 static struct dwc3_omap_device usb_otg_ss2_glue = {
596 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
597 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
601 static struct ti_usb_phy_device usb_phy2_device = {
602 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
606 int usb_gadget_handle_interrupts(int index)
610 status = dwc3_omap_uboot_interrupt_status(index);
612 dwc3_uboot_handle_interrupt(index);
616 #endif /* CONFIG_USB_DWC3 */
618 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
619 int board_usb_init(int index, enum usb_init_type init)
621 enable_usb_clocks(index);
624 if (init == USB_INIT_DEVICE) {
625 printf("port %d can't be used as device\n", index);
626 disable_usb_clocks(index);
631 if (init == USB_INIT_DEVICE) {
632 #ifdef CONFIG_USB_DWC3
633 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
634 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
635 ti_usb_phy_uboot_init(&usb_phy2_device);
636 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
637 dwc3_uboot_init(&usb_otg_ss2);
640 printf("port %d can't be used as host\n", index);
641 disable_usb_clocks(index);
647 printf("Invalid Controller Index\n");
653 int board_usb_cleanup(int index, enum usb_init_type init)
655 #ifdef CONFIG_USB_DWC3
659 if (init == USB_INIT_DEVICE) {
660 ti_usb_phy_uboot_exit(index);
661 dwc3_uboot_exit(index);
662 dwc3_omap_uboot_exit(index);
666 printf("Invalid Controller Index\n");
669 disable_usb_clocks(index);
672 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
674 #ifdef CONFIG_DRIVER_TI_CPSW
676 /* Delay value to add to calibrated value */
677 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
678 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
679 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
680 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
681 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
682 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
683 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
684 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
685 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
686 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
688 static void cpsw_control(int enabled)
690 /* VTP can be added here */
693 static struct cpsw_slave_data cpsw_slaves[] = {
695 .slave_reg_ofs = 0x208,
696 .sliver_reg_ofs = 0xd80,
700 .slave_reg_ofs = 0x308,
701 .sliver_reg_ofs = 0xdc0,
706 static struct cpsw_platform_data cpsw_data = {
707 .mdio_base = CPSW_MDIO_BASE,
708 .cpsw_base = CPSW_BASE,
711 .cpdma_reg_ofs = 0x800,
713 .slave_data = cpsw_slaves,
714 .ale_reg_ofs = 0xd00,
716 .host_port_reg_ofs = 0x108,
717 .hw_stats_reg_ofs = 0x900,
718 .bd_ram_ofs = 0x2000,
719 .mac_control = (1 << 5),
720 .control = cpsw_control,
722 .version = CPSW_CTRL_VERSION_2,
725 static u64 mac_to_u64(u8 mac[6])
730 for (i = 0; i < 6; i++) {
738 static void u64_to_mac(u64 addr, u8 mac[6])
748 int board_eth_init(bd_t *bis)
752 uint32_t mac_hi, mac_lo;
756 u8 mac_addr1[6], mac_addr2[6];
759 /* try reading mac address from efuse */
760 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
761 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
762 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
763 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
764 mac_addr[2] = mac_hi & 0xFF;
765 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
766 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
767 mac_addr[5] = mac_lo & 0xFF;
769 if (!getenv("ethaddr")) {
770 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
772 if (is_valid_ethaddr(mac_addr))
773 eth_setenv_enetaddr("ethaddr", mac_addr);
776 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
777 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
778 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
779 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
780 mac_addr[2] = mac_hi & 0xFF;
781 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
782 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
783 mac_addr[5] = mac_lo & 0xFF;
785 if (!getenv("eth1addr")) {
786 if (is_valid_ethaddr(mac_addr))
787 eth_setenv_enetaddr("eth1addr", mac_addr);
790 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
792 writel(ctrl_val, (*ctrl)->control_core_control_io1);
794 /* The phy address for the AM57xx IDK are different than x15 */
795 if (board_is_am572x_idk() || board_is_am571x_idk()) {
796 cpsw_data.slave_data[0].phy_addr = 0;
797 cpsw_data.slave_data[1].phy_addr = 1;
800 ret = cpsw_register(&cpsw_data);
802 printf("Error %d registering CPSW switch\n", ret);
805 * Export any Ethernet MAC addresses from EEPROM.
806 * On AM57xx the 2 MAC addresses define the address range
808 board_ti_get_eth_mac_addr(0, mac_addr1);
809 board_ti_get_eth_mac_addr(1, mac_addr2);
811 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
812 mac1 = mac_to_u64(mac_addr1);
813 mac2 = mac_to_u64(mac_addr2);
815 /* must contain an address range */
816 num_macs = mac2 - mac1 + 1;
817 /* <= 50 to protect against user programming error */
818 if (num_macs > 0 && num_macs <= 50) {
819 for (i = 0; i < num_macs; i++) {
820 u64_to_mac(mac1 + i, mac_addr);
821 if (is_valid_ethaddr(mac_addr)) {
822 eth_setenv_enetaddr_by_index("eth",
834 #ifdef CONFIG_BOARD_EARLY_INIT_F
835 /* VTT regulator enable */
836 static inline void vtt_regulator_enable(void)
838 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
841 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
842 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
845 int board_early_init_f(void)
847 vtt_regulator_enable();
852 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
853 int ft_board_setup(void *blob, bd_t *bd)
855 ft_cpu_setup(blob, bd);
861 #ifdef CONFIG_SPL_LOAD_FIT
862 int board_fit_config_name_match(const char *name)
864 if (board_is_x15()) {
865 if (board_is_x15_revb1()) {
866 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
868 } else if (!strcmp(name, "am57xx-beagle-x15")) {
871 } else if (board_is_am572x_evm() &&
872 !strcmp(name, "am57xx-beagle-x15")) {
874 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
876 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
884 #ifdef CONFIG_TI_SECURE_DEVICE
885 void board_fit_image_post_process(void **p_image, size_t *p_size)
887 secure_boot_verify_image(p_image, p_size);
890 void board_tee_image_process(ulong tee_image, size_t tee_size)
892 secure_tee_install((u32)tee_image);
895 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);