git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32
  33 #include "../common/board_detect.h"
  34 #include "mux_data.h"
  35
  36 #define board_is_x15()          board_ti_is("BBRDX15_")
  37 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  38
  39 #ifdef CONFIG_DRIVER_TI_CPSW
  40 #include <cpsw.h>
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /* GPIO 7_11 */
  46 #define GPIO_DDR_VTT_EN 203
  47
  48 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  49
  50 const struct omap_sysinfo sysinfo = {
  51         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  52 };
  53
  54 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  55         .dmm_lisa_map_3 = 0x80740300,
  56         .is_ma_present  = 0x1
  57 };
  58
  59 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  60 {
  61         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  62 }
  63
  64 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  65         .sdram_config_init      = 0x61851b32,
  66         .sdram_config           = 0x61851b32,
  67         .sdram_config2          = 0x08000000,
  68         .ref_ctrl               = 0x000040F1,
  69         .ref_ctrl_final         = 0x00001035,
  70         .sdram_tim1             = 0xcccf36ab,
  71         .sdram_tim2             = 0x308f7fda,
  72         .sdram_tim3             = 0x409f88a8,
  73         .read_idle_ctrl         = 0x00050000,
  74         .zq_config              = 0x5007190b,
  75         .temp_alert_config      = 0x00000000,
  76         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  77         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  78         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  79         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  80         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  81         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  82         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  83         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  84         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  85         .emif_rd_wr_lvl_ctl     = 0x00000000,
  86         .emif_rd_wr_exec_thresh = 0x00000305
  87 };
  88
  89 /* Ext phy ctrl regs 1-35 */
  90 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  91         0x10040100,
  92         0x00910091,
  93         0x00950095,
  94         0x009B009B,
  95         0x009E009E,
  96         0x00980098,
  97         0x00340034,
  98         0x00350035,
  99         0x00340034,
 100         0x00310031,
 101         0x00340034,
 102         0x007F007F,
 103         0x007F007F,
 104         0x007F007F,
 105         0x007F007F,
 106         0x007F007F,
 107         0x00480048,
 108         0x004A004A,
 109         0x00520052,
 110         0x00550055,
 111         0x00500050,
 112         0x00000000,
 113         0x00600020,
 114         0x40011080,
 115         0x08102040,
 116         0x0,
 117         0x0,
 118         0x0,
 119         0x0,
 120         0x0,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0
 126 };
 127
 128 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 129         .sdram_config_init      = 0x61851b32,
 130         .sdram_config           = 0x61851b32,
 131         .sdram_config2          = 0x08000000,
 132         .ref_ctrl               = 0x000040F1,
 133         .ref_ctrl_final         = 0x00001035,
 134         .sdram_tim1             = 0xcccf36ab,
 135         .sdram_tim2             = 0x308f7fda,
 136         .sdram_tim3             = 0x409f88a8,
 137         .read_idle_ctrl         = 0x00050000,
 138         .zq_config              = 0x5007190b,
 139         .temp_alert_config      = 0x00000000,
 140         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 141         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 142         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 143         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
 144         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
 145         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
 146         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
 147         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 148         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 149         .emif_rd_wr_lvl_ctl     = 0x00000000,
 150         .emif_rd_wr_exec_thresh = 0x00000305
 151 };
 152
 153 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 154         0x10040100,
 155         0x00910091,
 156         0x00950095,
 157         0x009B009B,
 158         0x009E009E,
 159         0x00980098,
 160         0x00340034,
 161         0x00350035,
 162         0x00340034,
 163         0x00310031,
 164         0x00340034,
 165         0x007F007F,
 166         0x007F007F,
 167         0x007F007F,
 168         0x007F007F,
 169         0x007F007F,
 170         0x00480048,
 171         0x004A004A,
 172         0x00520052,
 173         0x00550055,
 174         0x00500050,
 175         0x00000000,
 176         0x00600020,
 177         0x40011080,
 178         0x08102040,
 179         0x0,
 180         0x0,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0
 189 };
 190
 191 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 192 {
 193         switch (emif_nr) {
 194         case 1:
 195                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 196                 break;
 197         case 2:
 198                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 199                 break;
 200         }
 201 }
 202
 203 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 204 {
 205         switch (emif_nr) {
 206         case 1:
 207                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 208                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 209                 break;
 210         case 2:
 211                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 212                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 213                 break;
 214         }
 215 }
 216
 217 struct vcores_data beagle_x15_volts = {
 218         .mpu.value              = VDD_MPU_DRA752,
 219         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU_NOM,
 220         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 221         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 222         .mpu.pmic               = &tps659038,
 223
 224         .eve.value              = VDD_EVE_DRA752,
 225         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 226         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 227         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 228         .eve.pmic               = &tps659038,
 229
 230         .gpu.value              = VDD_GPU_DRA752,
 231         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU_NOM,
 232         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 233         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 234         .gpu.pmic               = &tps659038,
 235
 236         .core.value             = VDD_CORE_DRA752,
 237         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE_NOM,
 238         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 239         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 240         .core.pmic              = &tps659038,
 241
 242         .iva.value              = VDD_IVA_DRA752,
 243         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA_NOM,
 244         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 245         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 246         .iva.pmic               = &tps659038,
 247 };
 248
 249 #ifdef CONFIG_SPL_BUILD
 250 /* No env to setup for SPL */
 251 static inline void setup_board_eeprom_env(void) { }
 252
 253 /* Override function to read eeprom information */
 254 void do_board_detect(void)
 255 {
 256         int rc;
 257
 258         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 259                                   CONFIG_EEPROM_CHIP_ADDRESS);
 260         if (rc)
 261                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 262 }
 263
 264 #else   /* CONFIG_SPL_BUILD */
 265
 266 /* Override function to read eeprom information: actual i2c read done by SPL*/
 267 void do_board_detect(void)
 268 {
 269         char *bname = NULL;
 270         int rc;
 271
 272         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 273                                   CONFIG_EEPROM_CHIP_ADDRESS);
 274         if (rc)
 275                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 276
 277         if (board_is_x15())
 278                 bname = "BeagleBoard X15";
 279         else if (board_is_am572x_evm())
 280                 bname = "AM572x EVM";
 281
 282         if (bname)
 283                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 284                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 285 }
 286
 287 static void setup_board_eeprom_env(void)
 288 {
 289         char *name = "beagle_x15";
 290         int rc;
 291
 292         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 293                                   CONFIG_EEPROM_CHIP_ADDRESS);
 294         if (rc)
 295                 goto invalid_eeprom;
 296
 297         if (board_is_am572x_evm())
 298                 name = "am57xx_evm";
 299         else
 300                 printf("Unidentified board claims %s in eeprom header\n",
 301                        board_ti_get_name());
 302
 303 invalid_eeprom:
 304         set_board_info_env(name);
 305 }
 306
 307 #endif  /* CONFIG_SPL_BUILD */
 308
 309 void hw_data_init(void)
 310 {
 311         *prcm = &dra7xx_prcm;
 312         *dplls_data = &dra7xx_dplls;
 313         *omap_vcores = &beagle_x15_volts;
 314         *ctrl = &dra7xx_ctrl;
 315 }
 316
 317 int board_init(void)
 318 {
 319         gpmc_init();
 320         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 321
 322         return 0;
 323 }
 324
 325 int board_late_init(void)
 326 {
 327         init_sata(0);
 328         setup_board_eeprom_env();
 329
 330         /*
 331          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 332          * This is the POWERHOLD-in-Low behavior.
 333          */
 334         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 335         return 0;
 336 }
 337
 338 void set_muxconf_regs_essential(void)
 339 {
 340         do_set_mux32((*ctrl)->control_padconf_core_base,
 341                      early_padconf, ARRAY_SIZE(early_padconf));
 342 }
 343
 344 #ifdef CONFIG_IODELAY_RECALIBRATION
 345 void recalibrate_iodelay(void)
 346 {
 347         __recalibrate_iodelay(core_padconf_array_essential,
 348                               ARRAY_SIZE(core_padconf_array_essential),
 349                               iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
 350 }
 351 #endif
 352
 353 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 354 int board_mmc_init(bd_t *bis)
 355 {
 356         omap_mmc_init(0, 0, 0, -1, -1);
 357         omap_mmc_init(1, 0, 0, -1, -1);
 358         return 0;
 359 }
 360 #endif
 361
 362 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 363 int spl_start_uboot(void)
 364 {
 365         /* break into full u-boot on 'c' */
 366         if (serial_tstc() && serial_getc() == 'c')
 367                 return 1;
 368
 369 #ifdef CONFIG_SPL_ENV_SUPPORT
 370         env_init();
 371         env_relocate_spec();
 372         if (getenv_yesno("boot_os") != 1)
 373                 return 1;
 374 #endif
 375
 376         return 0;
 377 }
 378 #endif
 379
 380 #ifdef CONFIG_USB_DWC3
 381 static struct dwc3_device usb_otg_ss1 = {
 382         .maximum_speed = USB_SPEED_SUPER,
 383         .base = DRA7_USB_OTG_SS1_BASE,
 384         .tx_fifo_resize = false,
 385         .index = 0,
 386 };
 387
 388 static struct dwc3_omap_device usb_otg_ss1_glue = {
 389         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 390         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 391         .index = 0,
 392 };
 393
 394 static struct ti_usb_phy_device usb_phy1_device = {
 395         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 396         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 397         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 398         .index = 0,
 399 };
 400
 401 static struct dwc3_device usb_otg_ss2 = {
 402         .maximum_speed = USB_SPEED_HIGH,
 403         .base = DRA7_USB_OTG_SS2_BASE,
 404         .tx_fifo_resize = false,
 405         .index = 1,
 406 };
 407
 408 static struct dwc3_omap_device usb_otg_ss2_glue = {
 409         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 410         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 411         .index = 1,
 412 };
 413
 414 static struct ti_usb_phy_device usb_phy2_device = {
 415         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 416         .index = 1,
 417 };
 418
 419 int board_usb_init(int index, enum usb_init_type init)
 420 {
 421         enable_usb_clocks(index);
 422         switch (index) {
 423         case 0:
 424                 if (init == USB_INIT_DEVICE) {
 425                         printf("port %d can't be used as device\n", index);
 426                         disable_usb_clocks(index);
 427                         return -EINVAL;
 428                 } else {
 429                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 430                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 431                         setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 432                                      OTG_SS_CLKCTRL_MODULEMODE_HW |
 433                                      OPTFCLKEN_REFCLK960M);
 434                 }
 435
 436                 ti_usb_phy_uboot_init(&usb_phy1_device);
 437                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 438                 dwc3_uboot_init(&usb_otg_ss1);
 439                 break;
 440         case 1:
 441                 if (init == USB_INIT_DEVICE) {
 442                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 443                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 444                 } else {
 445                         printf("port %d can't be used as host\n", index);
 446                         disable_usb_clocks(index);
 447                         return -EINVAL;
 448                 }
 449
 450                 ti_usb_phy_uboot_init(&usb_phy2_device);
 451                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 452                 dwc3_uboot_init(&usb_otg_ss2);
 453                 break;
 454         default:
 455                 printf("Invalid Controller Index\n");
 456         }
 457
 458         return 0;
 459 }
 460
 461 int board_usb_cleanup(int index, enum usb_init_type init)
 462 {
 463         switch (index) {
 464         case 0:
 465         case 1:
 466                 ti_usb_phy_uboot_exit(index);
 467                 dwc3_uboot_exit(index);
 468                 dwc3_omap_uboot_exit(index);
 469                 break;
 470         default:
 471                 printf("Invalid Controller Index\n");
 472         }
 473         disable_usb_clocks(index);
 474         return 0;
 475 }
 476
 477 int usb_gadget_handle_interrupts(int index)
 478 {
 479         u32 status;
 480
 481         status = dwc3_omap_uboot_interrupt_status(index);
 482         if (status)
 483                 dwc3_uboot_handle_interrupt(index);
 484
 485         return 0;
 486 }
 487 #endif
 488
 489 #ifdef CONFIG_DRIVER_TI_CPSW
 490
 491 /* Delay value to add to calibrated value */
 492 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 493 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 494 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 495 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 496 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 497 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 498 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 499 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 500 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 501 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 502
 503 static void cpsw_control(int enabled)
 504 {
 505         /* VTP can be added here */
 506 }
 507
 508 static struct cpsw_slave_data cpsw_slaves[] = {
 509         {
 510                 .slave_reg_ofs  = 0x208,
 511                 .sliver_reg_ofs = 0xd80,
 512                 .phy_addr       = 1,
 513         },
 514         {
 515                 .slave_reg_ofs  = 0x308,
 516                 .sliver_reg_ofs = 0xdc0,
 517                 .phy_addr       = 2,
 518         },
 519 };
 520
 521 static struct cpsw_platform_data cpsw_data = {
 522         .mdio_base              = CPSW_MDIO_BASE,
 523         .cpsw_base              = CPSW_BASE,
 524         .mdio_div               = 0xff,
 525         .channels               = 8,
 526         .cpdma_reg_ofs          = 0x800,
 527         .slaves                 = 1,
 528         .slave_data             = cpsw_slaves,
 529         .ale_reg_ofs            = 0xd00,
 530         .ale_entries            = 1024,
 531         .host_port_reg_ofs      = 0x108,
 532         .hw_stats_reg_ofs       = 0x900,
 533         .bd_ram_ofs             = 0x2000,
 534         .mac_control            = (1 << 5),
 535         .control                = cpsw_control,
 536         .host_port_num          = 0,
 537         .version                = CPSW_CTRL_VERSION_2,
 538 };
 539
 540 int board_eth_init(bd_t *bis)
 541 {
 542         int ret;
 543         uint8_t mac_addr[6];
 544         uint32_t mac_hi, mac_lo;
 545         uint32_t ctrl_val;
 546
 547         /* try reading mac address from efuse */
 548         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 549         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 550         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 551         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 552         mac_addr[2] = mac_hi & 0xFF;
 553         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 554         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 555         mac_addr[5] = mac_lo & 0xFF;
 556
 557         if (!getenv("ethaddr")) {
 558                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 559
 560                 if (is_valid_ethaddr(mac_addr))
 561                         eth_setenv_enetaddr("ethaddr", mac_addr);
 562         }
 563
 564         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 565         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 566         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 567         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 568         mac_addr[2] = mac_hi & 0xFF;
 569         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 570         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 571         mac_addr[5] = mac_lo & 0xFF;
 572
 573         if (!getenv("eth1addr")) {
 574                 if (is_valid_ethaddr(mac_addr))
 575                         eth_setenv_enetaddr("eth1addr", mac_addr);
 576         }
 577
 578         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 579         ctrl_val |= 0x22;
 580         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 581
 582         ret = cpsw_register(&cpsw_data);
 583         if (ret < 0)
 584                 printf("Error %d registering CPSW switch\n", ret);
 585
 586         return ret;
 587 }
 588 #endif
 589
 590 #ifdef CONFIG_BOARD_EARLY_INIT_F
 591 /* VTT regulator enable */
 592 static inline void vtt_regulator_enable(void)
 593 {
 594         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 595                 return;
 596
 597         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 598         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 599 }
 600
 601 int board_early_init_f(void)
 602 {
 603         vtt_regulator_enable();
 604         return 0;
 605 }
 606 #endif