2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sata.h>
21 #include <asm/arch/gpio.h>
22 #include <environment.h>
26 #ifdef CONFIG_DRIVER_TI_CPSW
30 DECLARE_GLOBAL_DATA_PTR;
32 const struct omap_sysinfo sysinfo = {
33 "Board: BeagleBoard x15\n"
36 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
37 .dmm_lisa_map_3 = 0x80740300,
41 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
43 *dmm_lisa_regs = &beagle_x15_lisa_regs;
46 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
47 .sdram_config_init = 0x61851b32,
48 .sdram_config = 0x61851b32,
49 .sdram_config2 = 0x00000000,
50 .ref_ctrl = 0x000040F1,
51 .ref_ctrl_final = 0x00001035,
52 .sdram_tim1 = 0xceef266b,
53 .sdram_tim2 = 0x328f7fda,
54 .sdram_tim3 = 0x027f88a8,
55 .read_idle_ctrl = 0x00050001,
56 .zq_config = 0x0007190b,
57 .temp_alert_config = 0x00000000,
58 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
59 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
60 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
61 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
62 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
63 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
64 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
65 .emif_rd_wr_lvl_rmp_win = 0x00000000,
66 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
67 .emif_rd_wr_lvl_ctl = 0x00000000,
68 .emif_rd_wr_exec_thresh = 0x00000305
71 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
103 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
104 .sdram_config_init = 0x61851b32,
105 .sdram_config = 0x61851b32,
106 .sdram_config2 = 0x00000000,
107 .ref_ctrl = 0x000040F1,
108 .ref_ctrl_final = 0x00001035,
109 .sdram_tim1 = 0xceef266b,
110 .sdram_tim2 = 0x328f7fda,
111 .sdram_tim3 = 0x027f88a8,
112 .read_idle_ctrl = 0x00050001,
113 .zq_config = 0x0007190b,
114 .temp_alert_config = 0x00000000,
115 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
116 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
117 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
118 .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
119 .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
120 .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
121 .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
122 .emif_rd_wr_lvl_rmp_win = 0x00000000,
123 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
124 .emif_rd_wr_lvl_ctl = 0x00000000,
125 .emif_rd_wr_exec_thresh = 0x00000305
128 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
158 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
162 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
165 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
170 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
174 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
175 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
178 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
179 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
184 struct vcores_data beagle_x15_volts = {
185 .mpu.value = VDD_MPU_DRA752,
186 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
187 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
188 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
189 .mpu.pmic = &tps659038,
191 .eve.value = VDD_EVE_DRA752,
192 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
193 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
194 .eve.addr = TPS659038_REG_ADDR_SMPS45,
195 .eve.pmic = &tps659038,
197 .gpu.value = VDD_GPU_DRA752,
198 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
199 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
200 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
201 .gpu.pmic = &tps659038,
203 .core.value = VDD_CORE_DRA752,
204 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
205 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
206 .core.addr = TPS659038_REG_ADDR_SMPS6,
207 .core.pmic = &tps659038,
209 .iva.value = VDD_IVA_DRA752,
210 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
211 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
212 .iva.addr = TPS659038_REG_ADDR_SMPS45,
213 .iva.pmic = &tps659038,
216 void hw_data_init(void)
218 *prcm = &dra7xx_prcm;
219 *dplls_data = &dra7xx_dplls;
220 *omap_vcores = &beagle_x15_volts;
221 *ctrl = &dra7xx_ctrl;
227 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
232 int board_late_init(void)
236 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
237 * This is the POWERHOLD-in-Low behavior.
239 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
243 static void do_set_mux32(u32 base,
244 struct pad_conf_entry const *array, int size)
247 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
249 for (i = 0; i < size; i++, pad++)
250 writel(pad->val, base + pad->offset);
253 void set_muxconf_regs_essential(void)
255 do_set_mux32((*ctrl)->control_padconf_core_base,
256 core_padconf_array_essential,
257 sizeof(core_padconf_array_essential) /
258 sizeof(struct pad_conf_entry));
261 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
262 int board_mmc_init(bd_t *bis)
264 omap_mmc_init(0, 0, 0, -1, -1);
265 omap_mmc_init(1, 0, 0, -1, -1);
270 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
271 int spl_start_uboot(void)
273 /* break into full u-boot on 'c' */
274 if (serial_tstc() && serial_getc() == 'c')
277 #ifdef CONFIG_SPL_ENV_SUPPORT
280 if (getenv_yesno("boot_os") != 1)
288 #ifdef CONFIG_DRIVER_TI_CPSW
290 /* Delay value to add to calibrated value */
291 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
292 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
293 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
294 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
295 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
296 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
297 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
298 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
299 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
300 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
302 static void cpsw_control(int enabled)
304 /* VTP can be added here */
307 static struct cpsw_slave_data cpsw_slaves[] = {
309 .slave_reg_ofs = 0x208,
310 .sliver_reg_ofs = 0xd80,
314 .slave_reg_ofs = 0x308,
315 .sliver_reg_ofs = 0xdc0,
320 static struct cpsw_platform_data cpsw_data = {
321 .mdio_base = CPSW_MDIO_BASE,
322 .cpsw_base = CPSW_BASE,
325 .cpdma_reg_ofs = 0x800,
327 .slave_data = cpsw_slaves,
328 .ale_reg_ofs = 0xd00,
330 .host_port_reg_ofs = 0x108,
331 .hw_stats_reg_ofs = 0x900,
332 .bd_ram_ofs = 0x2000,
333 .mac_control = (1 << 5),
334 .control = cpsw_control,
336 .version = CPSW_CTRL_VERSION_2,
339 int board_eth_init(bd_t *bis)
343 uint32_t mac_hi, mac_lo;
346 /* try reading mac address from efuse */
347 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
348 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
349 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
350 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
351 mac_addr[2] = mac_hi & 0xFF;
352 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
353 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
354 mac_addr[5] = mac_lo & 0xFF;
356 if (!getenv("ethaddr")) {
357 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
359 if (is_valid_ethaddr(mac_addr))
360 eth_setenv_enetaddr("ethaddr", mac_addr);
363 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
364 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
365 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
366 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
367 mac_addr[2] = mac_hi & 0xFF;
368 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
369 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
370 mac_addr[5] = mac_lo & 0xFF;
372 if (!getenv("eth1addr")) {
373 if (is_valid_ethaddr(mac_addr))
374 eth_setenv_enetaddr("eth1addr", mac_addr);
377 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
379 writel(ctrl_val, (*ctrl)->control_core_control_io1);
381 ret = cpsw_register(&cpsw_data);
383 printf("Error %d registering CPSW switch\n", ret);