3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/usb/gadget.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <environment.h>
25 #include <dwc3-uboot.h>
26 #include <dwc3-omap-uboot.h>
27 #include <ti-usb-phy-uboot.h>
31 #ifdef CONFIG_DRIVER_TI_CPSW
35 DECLARE_GLOBAL_DATA_PTR;
38 #define GPIO_DDR_VTT_EN 203
40 const struct omap_sysinfo sysinfo = {
52 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
57 int board_late_init(void)
59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
62 if (omap_revision() == DRA722_ES1_0)
63 setenv("board_name", "dra72x");
65 setenv("board_name", "dra7xx");
67 id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
68 id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
69 usb_set_serial_num_from_die_id(id);
74 void set_muxconf_regs_essential(void)
76 do_set_mux32((*ctrl)->control_padconf_core_base,
77 early_padconf, ARRAY_SIZE(early_padconf));
80 #ifdef CONFIG_IODELAY_RECALIBRATION
81 void recalibrate_iodelay(void)
83 struct pad_conf_entry const *pads;
84 struct iodelay_cfg_entry const *iodelay;
87 switch (omap_revision()) {
89 pads = core_padconf_array_essential;
90 npads = ARRAY_SIZE(core_padconf_array_essential);
91 iodelay = iodelay_cfg_array;
92 niodelays = ARRAY_SIZE(iodelay_cfg_array);
96 pads = dra74x_core_padconf_array;
97 npads = ARRAY_SIZE(dra74x_core_padconf_array);
98 iodelay = dra742_es1_1_iodelay_cfg_array;
99 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
103 pads = dra74x_core_padconf_array;
104 npads = ARRAY_SIZE(dra74x_core_padconf_array);
105 iodelay = dra742_es2_0_iodelay_cfg_array;
106 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
107 /* Setup port1 and port2 for rgmii with 'no-id' mode */
108 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
109 RGMII1_ID_MODE_N_MASK);
112 __recalibrate_iodelay(pads, npads, iodelay, niodelays);
116 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
117 int board_mmc_init(bd_t *bis)
119 omap_mmc_init(0, 0, 0, -1, -1);
120 omap_mmc_init(1, 0, 0, -1, -1);
125 #ifdef CONFIG_USB_DWC3
126 static struct dwc3_device usb_otg_ss1 = {
127 .maximum_speed = USB_SPEED_SUPER,
128 .base = DRA7_USB_OTG_SS1_BASE,
129 .tx_fifo_resize = false,
133 static struct dwc3_omap_device usb_otg_ss1_glue = {
134 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
135 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
139 static struct ti_usb_phy_device usb_phy1_device = {
140 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
141 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
142 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
146 static struct dwc3_device usb_otg_ss2 = {
147 .maximum_speed = USB_SPEED_SUPER,
148 .base = DRA7_USB_OTG_SS2_BASE,
149 .tx_fifo_resize = false,
153 static struct dwc3_omap_device usb_otg_ss2_glue = {
154 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
155 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
159 static struct ti_usb_phy_device usb_phy2_device = {
160 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
164 int board_usb_init(int index, enum usb_init_type init)
166 enable_usb_clocks(index);
169 if (init == USB_INIT_DEVICE) {
170 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
171 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
173 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
174 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
177 ti_usb_phy_uboot_init(&usb_phy1_device);
178 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
179 dwc3_uboot_init(&usb_otg_ss1);
182 if (init == USB_INIT_DEVICE) {
183 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
184 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
186 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
187 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
190 ti_usb_phy_uboot_init(&usb_phy2_device);
191 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
192 dwc3_uboot_init(&usb_otg_ss2);
195 printf("Invalid Controller Index\n");
201 int board_usb_cleanup(int index, enum usb_init_type init)
206 ti_usb_phy_uboot_exit(index);
207 dwc3_uboot_exit(index);
208 dwc3_omap_uboot_exit(index);
211 printf("Invalid Controller Index\n");
213 disable_usb_clocks(index);
217 int usb_gadget_handle_interrupts(int index)
221 status = dwc3_omap_uboot_interrupt_status(index);
223 dwc3_uboot_handle_interrupt(index);
229 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
230 int spl_start_uboot(void)
232 /* break into full u-boot on 'c' */
233 if (serial_tstc() && serial_getc() == 'c')
236 #ifdef CONFIG_SPL_ENV_SUPPORT
239 if (getenv_yesno("boot_os") != 1)
247 #ifdef CONFIG_DRIVER_TI_CPSW
248 extern u32 *const omap_si_rev;
250 static void cpsw_control(int enabled)
252 /* VTP can be added here */
257 static struct cpsw_slave_data cpsw_slaves[] = {
259 .slave_reg_ofs = 0x208,
260 .sliver_reg_ofs = 0xd80,
264 .slave_reg_ofs = 0x308,
265 .sliver_reg_ofs = 0xdc0,
270 static struct cpsw_platform_data cpsw_data = {
271 .mdio_base = CPSW_MDIO_BASE,
272 .cpsw_base = CPSW_BASE,
275 .cpdma_reg_ofs = 0x800,
277 .slave_data = cpsw_slaves,
278 .ale_reg_ofs = 0xd00,
280 .host_port_reg_ofs = 0x108,
281 .hw_stats_reg_ofs = 0x900,
282 .bd_ram_ofs = 0x2000,
283 .mac_control = (1 << 5),
284 .control = cpsw_control,
286 .version = CPSW_CTRL_VERSION_2,
289 int board_eth_init(bd_t *bis)
293 uint32_t mac_hi, mac_lo;
296 /* try reading mac address from efuse */
297 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
298 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
299 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
300 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
301 mac_addr[2] = mac_hi & 0xFF;
302 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
303 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
304 mac_addr[5] = mac_lo & 0xFF;
306 if (!getenv("ethaddr")) {
307 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
309 if (is_valid_ethaddr(mac_addr))
310 eth_setenv_enetaddr("ethaddr", mac_addr);
313 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
314 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
315 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
316 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
317 mac_addr[2] = mac_hi & 0xFF;
318 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
319 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
320 mac_addr[5] = mac_lo & 0xFF;
322 if (!getenv("eth1addr")) {
323 if (is_valid_ethaddr(mac_addr))
324 eth_setenv_enetaddr("eth1addr", mac_addr);
327 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
329 writel(ctrl_val, (*ctrl)->control_core_control_io1);
331 if (*omap_si_rev == DRA722_ES1_0)
332 cpsw_data.active_slave = 1;
334 ret = cpsw_register(&cpsw_data);
336 printf("Error %d registering CPSW switch\n", ret);
342 #ifdef CONFIG_BOARD_EARLY_INIT_F
343 /* VTT regulator enable */
344 static inline void vtt_regulator_enable(void)
346 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
349 /* Do not enable VTT for DRA722 */
350 if (omap_revision() == DRA722_ES1_0)
354 * EVM Rev G and later use gpio7_11 for DDR3 termination.
355 * This is safe enough to do on older revs.
357 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
358 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
361 int board_early_init_f(void)
363 vtt_regulator_enable();