3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/string.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/dra7xx_iodelay.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sata.h>
26 #include <environment.h>
27 #include <dwc3-uboot.h>
28 #include <dwc3-omap-uboot.h>
29 #include <ti-usb-phy-uboot.h>
32 #include "../common/board_detect.h"
34 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
35 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
36 (strncmp("H", board_ti_get_rev(), 1) <= 0)
38 #ifdef CONFIG_DRIVER_TI_CPSW
42 DECLARE_GLOBAL_DATA_PTR;
45 #define GPIO_DDR_VTT_EN 203
47 #define SYSINFO_BOARD_NAME_MAX_LEN 37
49 const struct omap_sysinfo sysinfo = {
50 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
53 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
54 .sdram_config_init = 0x61851ab2,
55 .sdram_config = 0x61851ab2,
56 .sdram_config2 = 0x08000000,
57 .ref_ctrl = 0x000040F1,
58 .ref_ctrl_final = 0x00001035,
59 .sdram_tim1 = 0xCCCF36B3,
60 .sdram_tim2 = 0x308F7FDA,
61 .sdram_tim3 = 0x427F88A8,
62 .read_idle_ctrl = 0x00050000,
63 .zq_config = 0x0007190B,
64 .temp_alert_config = 0x00000000,
65 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
66 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
67 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
68 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
69 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
70 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
71 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
72 .emif_rd_wr_lvl_rmp_win = 0x00000000,
73 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
74 .emif_rd_wr_lvl_ctl = 0x00000000,
75 .emif_rd_wr_exec_thresh = 0x00000305
78 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
79 .sdram_config_init = 0x61851B32,
80 .sdram_config = 0x61851B32,
81 .sdram_config2 = 0x08000000,
82 .ref_ctrl = 0x000040F1,
83 .ref_ctrl_final = 0x00001035,
84 .sdram_tim1 = 0xCCCF36B3,
85 .sdram_tim2 = 0x308F7FDA,
86 .sdram_tim3 = 0x427F88A8,
87 .read_idle_ctrl = 0x00050000,
88 .zq_config = 0x0007190B,
89 .temp_alert_config = 0x00000000,
90 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
91 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
92 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
93 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
94 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
95 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
96 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
97 .emif_rd_wr_lvl_rmp_win = 0x00000000,
98 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
99 .emif_rd_wr_lvl_ctl = 0x00000000,
100 .emif_rd_wr_exec_thresh = 0x00000305
103 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
104 .sdram_config_init = 0x61862B32,
105 .sdram_config = 0x61862B32,
106 .sdram_config2 = 0x08000000,
107 .ref_ctrl = 0x0000514C,
108 .ref_ctrl_final = 0x0000144A,
109 .sdram_tim1 = 0xD113781C,
110 .sdram_tim2 = 0x30717FE3,
111 .sdram_tim3 = 0x409F86A8,
112 .read_idle_ctrl = 0x00050000,
113 .zq_config = 0x5007190B,
114 .temp_alert_config = 0x00000000,
115 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
116 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
117 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
118 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
119 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
120 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
121 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
122 .emif_rd_wr_lvl_rmp_win = 0x00000000,
123 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
124 .emif_rd_wr_lvl_ctl = 0x00000000,
125 .emif_rd_wr_exec_thresh = 0x00000305
128 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
130 switch (omap_revision()) {
136 *regs = &emif1_ddr3_532_mhz_1cs;
139 *regs = &emif2_ddr3_532_mhz_1cs;
144 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
147 *regs = &emif1_ddr3_532_mhz_1cs;
151 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
152 .dmm_lisa_map_0 = 0x0,
153 .dmm_lisa_map_1 = 0x80640300,
154 .dmm_lisa_map_2 = 0xC0500220,
155 .dmm_lisa_map_3 = 0xFF020100,
159 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
160 .dmm_lisa_map_0 = 0x0,
161 .dmm_lisa_map_1 = 0x0,
162 .dmm_lisa_map_2 = 0x80600100,
163 .dmm_lisa_map_3 = 0xFF020100,
167 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
169 switch (omap_revision()) {
173 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
177 *dmm_lisa_regs = &lisa_map_2G_x_2;
189 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
194 int board_late_init(void)
196 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
197 char *name = "unknown";
204 set_board_info_env(name);
206 omap_die_id_serial();
211 #ifdef CONFIG_SPL_BUILD
212 void do_board_detect(void)
216 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
217 CONFIG_EEPROM_CHIP_ADDRESS);
219 printf("ti_i2c_eeprom_init failed %d\n", rc);
224 void do_board_detect(void)
229 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
230 CONFIG_EEPROM_CHIP_ADDRESS);
232 printf("ti_i2c_eeprom_init failed %d\n", rc);
234 if (board_is_dra74x_evm()) {
235 bname = "DRA74x EVM";
236 /* If EEPROM is not populated */
239 bname = "DRA72x EVM";
241 bname = "DRA74x EVM";
245 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
246 "Board: %s REV %s\n", bname, board_ti_get_rev());
248 #endif /* CONFIG_SPL_BUILD */
250 void set_muxconf_regs_essential(void)
252 do_set_mux32((*ctrl)->control_padconf_core_base,
253 early_padconf, ARRAY_SIZE(early_padconf));
256 #ifdef CONFIG_IODELAY_RECALIBRATION
257 void recalibrate_iodelay(void)
259 struct pad_conf_entry const *pads;
260 struct iodelay_cfg_entry const *iodelay;
261 int npads, niodelays;
263 switch (omap_revision()) {
265 pads = core_padconf_array_essential;
266 npads = ARRAY_SIZE(core_padconf_array_essential);
267 iodelay = iodelay_cfg_array;
268 niodelays = ARRAY_SIZE(iodelay_cfg_array);
272 pads = dra74x_core_padconf_array;
273 npads = ARRAY_SIZE(dra74x_core_padconf_array);
274 iodelay = dra742_es1_1_iodelay_cfg_array;
275 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
279 pads = dra74x_core_padconf_array;
280 npads = ARRAY_SIZE(dra74x_core_padconf_array);
281 iodelay = dra742_es2_0_iodelay_cfg_array;
282 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
283 /* Setup port1 and port2 for rgmii with 'no-id' mode */
284 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
285 RGMII1_ID_MODE_N_MASK);
288 __recalibrate_iodelay(pads, npads, iodelay, niodelays);
292 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
293 int board_mmc_init(bd_t *bis)
295 omap_mmc_init(0, 0, 0, -1, -1);
296 omap_mmc_init(1, 0, 0, -1, -1);
301 #ifdef CONFIG_USB_DWC3
302 static struct dwc3_device usb_otg_ss1 = {
303 .maximum_speed = USB_SPEED_SUPER,
304 .base = DRA7_USB_OTG_SS1_BASE,
305 .tx_fifo_resize = false,
309 static struct dwc3_omap_device usb_otg_ss1_glue = {
310 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
311 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
315 static struct ti_usb_phy_device usb_phy1_device = {
316 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
317 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
318 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
322 static struct dwc3_device usb_otg_ss2 = {
323 .maximum_speed = USB_SPEED_SUPER,
324 .base = DRA7_USB_OTG_SS2_BASE,
325 .tx_fifo_resize = false,
329 static struct dwc3_omap_device usb_otg_ss2_glue = {
330 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
331 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
335 static struct ti_usb_phy_device usb_phy2_device = {
336 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
340 int board_usb_init(int index, enum usb_init_type init)
342 enable_usb_clocks(index);
345 if (init == USB_INIT_DEVICE) {
346 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
347 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
349 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
350 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
353 ti_usb_phy_uboot_init(&usb_phy1_device);
354 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
355 dwc3_uboot_init(&usb_otg_ss1);
358 if (init == USB_INIT_DEVICE) {
359 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
360 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
362 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
363 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
366 ti_usb_phy_uboot_init(&usb_phy2_device);
367 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
368 dwc3_uboot_init(&usb_otg_ss2);
371 printf("Invalid Controller Index\n");
377 int board_usb_cleanup(int index, enum usb_init_type init)
382 ti_usb_phy_uboot_exit(index);
383 dwc3_uboot_exit(index);
384 dwc3_omap_uboot_exit(index);
387 printf("Invalid Controller Index\n");
389 disable_usb_clocks(index);
393 int usb_gadget_handle_interrupts(int index)
397 status = dwc3_omap_uboot_interrupt_status(index);
399 dwc3_uboot_handle_interrupt(index);
405 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
406 int spl_start_uboot(void)
408 /* break into full u-boot on 'c' */
409 if (serial_tstc() && serial_getc() == 'c')
412 #ifdef CONFIG_SPL_ENV_SUPPORT
415 if (getenv_yesno("boot_os") != 1)
423 #ifdef CONFIG_DRIVER_TI_CPSW
424 extern u32 *const omap_si_rev;
426 static void cpsw_control(int enabled)
428 /* VTP can be added here */
433 static struct cpsw_slave_data cpsw_slaves[] = {
435 .slave_reg_ofs = 0x208,
436 .sliver_reg_ofs = 0xd80,
440 .slave_reg_ofs = 0x308,
441 .sliver_reg_ofs = 0xdc0,
446 static struct cpsw_platform_data cpsw_data = {
447 .mdio_base = CPSW_MDIO_BASE,
448 .cpsw_base = CPSW_BASE,
451 .cpdma_reg_ofs = 0x800,
453 .slave_data = cpsw_slaves,
454 .ale_reg_ofs = 0xd00,
456 .host_port_reg_ofs = 0x108,
457 .hw_stats_reg_ofs = 0x900,
458 .bd_ram_ofs = 0x2000,
459 .mac_control = (1 << 5),
460 .control = cpsw_control,
462 .version = CPSW_CTRL_VERSION_2,
465 int board_eth_init(bd_t *bis)
469 uint32_t mac_hi, mac_lo;
472 /* try reading mac address from efuse */
473 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
474 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
475 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
476 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
477 mac_addr[2] = mac_hi & 0xFF;
478 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
479 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
480 mac_addr[5] = mac_lo & 0xFF;
482 if (!getenv("ethaddr")) {
483 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
485 if (is_valid_ethaddr(mac_addr))
486 eth_setenv_enetaddr("ethaddr", mac_addr);
489 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
490 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
491 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
492 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
493 mac_addr[2] = mac_hi & 0xFF;
494 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
495 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
496 mac_addr[5] = mac_lo & 0xFF;
498 if (!getenv("eth1addr")) {
499 if (is_valid_ethaddr(mac_addr))
500 eth_setenv_enetaddr("eth1addr", mac_addr);
503 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
505 writel(ctrl_val, (*ctrl)->control_core_control_io1);
507 if (*omap_si_rev == DRA722_ES1_0)
508 cpsw_data.active_slave = 1;
510 ret = cpsw_register(&cpsw_data);
512 printf("Error %d registering CPSW switch\n", ret);
518 #ifdef CONFIG_BOARD_EARLY_INIT_F
519 /* VTT regulator enable */
520 static inline void vtt_regulator_enable(void)
522 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
525 /* Do not enable VTT for DRA722 */
526 if (omap_revision() == DRA722_ES1_0)
530 * EVM Rev G and later use gpio7_11 for DDR3 termination.
531 * This is safe enough to do on older revs.
533 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
534 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
537 int board_early_init_f(void)
539 vtt_regulator_enable();