2 * (C) Copyright 2004-2011
3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mem.h>
34 #include <asm/arch/mux.h>
35 #include <asm/arch/sys_proto.h>
36 #include <asm/arch/mmc_host_def.h>
39 #include <asm/mach-types.h>
40 #include <linux/mtd/nand.h>
43 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
44 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
46 DECLARE_GLOBAL_DATA_PTR;
48 static u32 omap3_evm_version;
50 u32 get_omap3_evm_rev(void)
52 return omap3_evm_version;
55 static void omap3_evm_get_revision(void)
57 #if defined(CONFIG_CMD_NET)
59 * Board revision can be ascertained only by identifying
60 * the Ethernet chipset.
64 /* Ethernet PHY ID is stored at ID_REV register */
65 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
66 printf("Read back SMSC id 0x%x\n", smsc_id);
69 /* SMSC9115 chipset */
71 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
73 /* SMSC 9220 chipset */
76 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
79 #if defined(CONFIG_STATIC_BOARD_REV)
81 * Look for static defintion of the board revision
83 omap3_evm_version = CONFIG_STATIC_BOARD_REV;
86 * Fallback to the default above.
88 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
90 #endif /* CONFIG_CMD_NET */
93 #ifdef CONFIG_USB_OMAP3
95 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
97 u8 omap3_evm_need_extvbus(void)
101 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
109 * Routine: board_init
110 * Description: Early hardware init.
114 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
115 /* board id for Linux */
116 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
117 /* boot param addr */
118 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
123 #ifdef CONFIG_SPL_BUILD
125 * Routine: get_board_mem_timings
126 * Description: If we use SPL then there is no x-loader nor config header
127 * so we have to setup the DDR timings ourself on the first bank. This
128 * provides the timing values back to the function that configures
131 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
137 * We need to identify what PoP memory is on the board so that
138 * we know what timings to use. To map the ID values please see
141 identify_nand_chip(&pop_mfr, &pop_id);
143 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
145 *mcfg = HYNIX_V_MCFG_200(256 << 20);
146 *ctrla = HYNIX_V_ACTIMA_200;
147 *ctrlb = HYNIX_V_ACTIMB_200;
150 *mcfg = MICRON_V_MCFG_165(128 << 20);
151 *ctrla = MICRON_V_ACTIMA_165;
152 *ctrlb = MICRON_V_ACTIMB_165;
154 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
155 *mr = MICRON_V_MR_165;
160 * Routine: misc_init_r
161 * Description: Init ethernet (done here so udelay works)
163 int misc_init_r(void)
166 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
167 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
170 #if defined(CONFIG_CMD_NET)
173 omap3_evm_get_revision();
175 #if defined(CONFIG_CMD_NET)
184 * Routine: set_muxconf_regs
185 * Description: Setting up the configuration Mux registers specific to the
186 * hardware. Many pins need to be moved from protect to primary
189 void set_muxconf_regs(void)
194 #ifdef CONFIG_CMD_NET
196 * Routine: setup_net_chip
197 * Description: Setting up the configuration GPMC registers specific to the
200 static void setup_net_chip(void)
202 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
204 /* Configure GPMC registers */
205 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
206 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
207 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
208 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
209 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
210 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
211 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
213 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
214 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
215 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
216 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
217 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
218 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
219 &ctrl_base->gpmc_nadv_ale);
223 * Reset the ethernet chip.
225 static void reset_net_chip(void)
230 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
231 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
233 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
236 ret = gpio_request(rst_gpio, "");
238 printf("Unable to get GPIO %d\n", rst_gpio);
242 /* Configure as output */
243 gpio_direction_output(rst_gpio, 0);
245 /* Send a pulse on the GPIO pin */
246 gpio_set_value(rst_gpio, 1);
248 gpio_set_value(rst_gpio, 0);
250 gpio_set_value(rst_gpio, 1);
253 int board_eth_init(bd_t *bis)
256 #ifdef CONFIG_SMC911X
257 #define STR_ENV_ETHADDR "ethaddr"
259 struct eth_device *dev;
262 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
264 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
265 dev = eth_get_dev_by_index(0);
267 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
269 printf("omap3evm: Couldn't get eth device\n");
276 #endif /* CONFIG_CMD_NET */
278 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
279 int board_mmc_init(bd_t *bis)
281 omap_mmc_init(0, 0, 0);