2 * K2G EVM : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/ti-common/keystone_net.h>
12 #include <asm/arch/psc_defs.h>
13 #include <asm/arch/mmc_host_def.h>
16 #include <remoteproc.h>
18 #include "../common/board_detect.h"
20 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
22 const unsigned int sysclk_array[MAX_SYSCLK] = {
29 unsigned int get_external_clk(u32 clk)
31 unsigned int clk_freq;
32 u8 sysclk_index = get_sysclk_index();
36 clk_freq = sysclk_array[sysclk_index];
39 clk_freq = sysclk_array[sysclk_index];
42 clk_freq = sysclk_array[sysclk_index];
45 clk_freq = sysclk_array[sysclk_index];
48 clk_freq = sysclk_array[sysclk_index];
58 int speeds[DEVSPEED_NUMSPDS] = {
71 static int dev_speeds[DEVSPEED_NUMSPDS] = {
82 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
84 [SPD400] = {MAIN_PLL, 125, 3, 2},
85 [SPD600] = {MAIN_PLL, 125, 2, 2},
86 [SPD800] = {MAIN_PLL, 250, 3, 2},
87 [SPD900] = {MAIN_PLL, 187, 2, 2},
88 [SPD1000] = {MAIN_PLL, 104, 1, 2},
91 [SPD400] = {MAIN_PLL, 100, 3, 2},
92 [SPD600] = {MAIN_PLL, 300, 6, 2},
93 [SPD800] = {MAIN_PLL, 200, 3, 2},
94 [SPD900] = {MAIN_PLL, 75, 1, 2},
95 [SPD1000] = {MAIN_PLL, 250, 3, 2},
98 [SPD400] = {MAIN_PLL, 32, 1, 2},
99 [SPD600] = {MAIN_PLL, 48, 1, 2},
100 [SPD800] = {MAIN_PLL, 64, 1, 2},
101 [SPD900] = {MAIN_PLL, 72, 1, 2},
102 [SPD1000] = {MAIN_PLL, 80, 1, 2},
105 [SPD400] = {MAIN_PLL, 400, 13, 2},
106 [SPD600] = {MAIN_PLL, 230, 5, 2},
107 [SPD800] = {MAIN_PLL, 123, 2, 2},
108 [SPD900] = {MAIN_PLL, 69, 1, 2},
109 [SPD1000] = {MAIN_PLL, 384, 5, 2},
113 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
115 [SPD200] = {TETRIS_PLL, 625, 6, 10},
116 [SPD400] = {TETRIS_PLL, 125, 1, 6},
117 [SPD600] = {TETRIS_PLL, 125, 1, 4},
118 [SPD800] = {TETRIS_PLL, 333, 2, 4},
119 [SPD900] = {TETRIS_PLL, 187, 2, 2},
120 [SPD1000] = {TETRIS_PLL, 104, 1, 2},
123 [SPD200] = {TETRIS_PLL, 250, 3, 10},
124 [SPD400] = {TETRIS_PLL, 100, 1, 6},
125 [SPD600] = {TETRIS_PLL, 100, 1, 4},
126 [SPD800] = {TETRIS_PLL, 400, 3, 4},
127 [SPD900] = {TETRIS_PLL, 75, 1, 2},
128 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
131 [SPD200] = {TETRIS_PLL, 80, 1, 10},
132 [SPD400] = {TETRIS_PLL, 96, 1, 6},
133 [SPD600] = {TETRIS_PLL, 96, 1, 4},
134 [SPD800] = {TETRIS_PLL, 128, 1, 4},
135 [SPD900] = {TETRIS_PLL, 72, 1, 2},
136 [SPD1000] = {TETRIS_PLL, 80, 1, 2},
139 [SPD200] = {TETRIS_PLL, 307, 4, 10},
140 [SPD400] = {TETRIS_PLL, 369, 4, 6},
141 [SPD600] = {TETRIS_PLL, 369, 4, 4},
142 [SPD800] = {TETRIS_PLL, 123, 1, 4},
143 [SPD900] = {TETRIS_PLL, 69, 1, 2},
144 [SPD1000] = {TETRIS_PLL, 384, 5, 2},
148 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
149 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
150 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
151 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
152 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
155 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
156 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
157 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
158 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
159 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
162 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
163 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
164 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
165 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
166 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
169 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
170 [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
171 [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
172 [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
173 [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
176 struct pll_init_data *get_pll_init_data(int pll)
179 struct pll_init_data *data = NULL;
180 u8 sysclk_index = get_sysclk_index();
184 speed = get_max_dev_speed(dev_speeds);
185 data = &main_pll_config[sysclk_index][speed];
188 speed = get_max_arm_speed(speeds);
189 data = &tetris_pll_config[sysclk_index][speed];
192 data = &nss_pll_config[sysclk_index];
195 data = &uart_pll_config[sysclk_index];
198 if (cpu_revision() & CPU_66AK2G1x) {
199 speed = get_max_arm_speed(speeds);
200 if (speed == SPD1000)
201 data = &ddr3_pll_config_1066[sysclk_index];
203 data = &ddr3_pll_config_800[sysclk_index];
205 data = &ddr3_pll_config_800[sysclk_index];
216 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
219 #if defined(CONFIG_MMC)
220 int board_mmc_init(bd_t *bis)
222 if (psc_enable_module(KS2_LPSC_MMC)) {
223 printf("%s module enabled failed\n", __func__);
227 if (board_is_k2g_gp() || board_is_k2g_g1())
228 omap_mmc_init(0, 0, 0, -1, -1);
230 omap_mmc_init(1, 0, 0, -1, -1);
235 #if defined(CONFIG_MULTI_DTB_FIT)
236 int board_fit_config_name_match(const char *name)
238 bool eeprom_read = board_ti_was_eeprom_read();
240 if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
242 else if (!strcmp(name, "keystone-k2g-evm") &&
243 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
245 else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
252 #if defined(CONFIG_DTB_RESELECT)
253 static int k2g_alt_board_detect(void)
257 rc = i2c_set_bus_num(1);
261 rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
265 ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
270 static void k2g_reset_mux_config(void)
272 /* Unlock the reset mux register */
273 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
275 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
276 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
277 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
279 /* lock the reset mux register to prevent any spurious writes. */
280 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
283 int embedded_dtb_select(void)
286 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
287 CONFIG_EEPROM_CHIP_ADDRESS);
289 rc = k2g_alt_board_detect();
291 printf("Unable to do board detection\n");
300 k2g_reset_mux_config();
302 if (board_is_k2g_gp() || board_is_k2g_g1()) {
303 /* deassert FLASH_HOLD */
304 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
306 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
314 #ifdef CONFIG_BOARD_LATE_INIT
315 int board_late_init(void)
317 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
320 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
321 CONFIG_EEPROM_CHIP_ADDRESS);
323 printf("ti_i2c_eeprom_init failed %d\n", rc);
325 board_ti_set_ethaddr(1);
328 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
329 if (board_is_k2g_gp())
330 env_set("board_name", "66AK2GGP\0");
331 else if (board_is_k2g_g1())
332 env_set("board_name", "66AK2GG1\0");
333 else if (board_is_k2g_ice())
334 env_set("board_name", "66AK2GIC\0");
340 #ifdef CONFIG_BOARD_EARLY_INIT_F
341 int board_early_init_f(void)
351 #ifdef CONFIG_SPL_BUILD
352 void spl_init_keystone_plls(void)
358 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
359 struct eth_priv_t eth_priv_cfg[] = {
361 .int_name = "K2G_EMAC",
365 .sgmii_link_type = SGMII_LINK_MAC_PHY,
366 .phy_if = PHY_INTERFACE_MODE_RGMII,
370 int get_num_eth_ports(void)
372 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
376 #ifdef CONFIG_TI_SECURE_DEVICE
377 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
379 int id = env_get_ulong("dev_pmmc", 10, 0);
382 if (!rproc_is_initialized())
385 ret = rproc_load(id, pmmc_image, pmmc_size);
386 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
387 id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
393 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);