2 * K2G: DDR3 initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ddr3.h>
15 /* K2G GP EVM DDR3 Configuration */
16 struct ddr3_phy_config ddr3phy_800_2g = {
17 .pllcr = 0x000DC000ul,
18 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
19 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
25 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
26 .dcr_val = ((1 << 10)),
27 .dtpr0 = 0x550F6644ul,
28 .dtpr1 = 0x328341E0ul,
29 .dtpr2 = 0x50022A00ul,
34 .pgcr2 = 0x00F03D09ul,
35 .zq0cr1 = 0x0001005Dul,
36 .zq1cr1 = 0x0001005Bul,
37 .zq2cr1 = 0x0001005Bul,
38 .pir_v1 = 0x00000033ul,
44 .datx8_4_val = ((1 << 0)),
45 .datx8_5_mask = DXEN_MASK,
47 .datx8_6_mask = DXEN_MASK,
49 .datx8_7_mask = DXEN_MASK,
51 .datx8_8_mask = DXEN_MASK,
53 .pir_v2 = 0x00000F81ul,
56 struct ddr3_emif_config ddr3_800_2g = {
57 .sdcfg = 0x62005662ul,
58 .sdtim1 = 0x0A385033ul,
59 .sdtim2 = 0x00001CA5ul,
60 .sdtim3 = 0x21ADFF32ul,
61 .sdtim4 = 0x533F067Ful,
62 .zqcfg = 0x70073200ul,
63 .sdrfc = 0x00000C34ul,
66 /* K2G ICE evm DDR3 Configuration */
67 struct ddr3_phy_config ddr3phy_800_512mb = {
68 .pllcr = 0x000DC000ul,
69 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
70 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
76 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
77 .dcr_val = ((1 << 10)),
78 .dtpr0 = 0x550E6644ul,
79 .dtpr1 = 0x32834200ul,
80 .dtpr2 = 0x50022A00ul,
85 .pgcr2 = 0x00F03D09ul,
86 .zq0cr1 = 0x0001005Dul,
87 .zq1cr1 = 0x0001005Bul,
88 .zq2cr1 = 0x0001005Bul,
89 .pir_v1 = 0x00000033ul,
90 .datx8_2_mask = DXEN_MASK,
92 .datx8_3_mask = DXEN_MASK,
94 .datx8_4_mask = DXEN_MASK,
96 .datx8_5_mask = DXEN_MASK,
98 .datx8_6_mask = DXEN_MASK,
100 .datx8_7_mask = DXEN_MASK,
102 .datx8_8_mask = DXEN_MASK,
104 .pir_v2 = 0x00000F81ul,
107 struct ddr3_emif_config ddr3_800_512mb = {
108 .sdcfg = 0x62006662ul,
109 .sdtim1 = 0x0A385033ul,
110 .sdtim2 = 0x00001CA5ul,
111 .sdtim3 = 0x21ADFF32ul,
112 .sdtim4 = 0x533F067Ful,
113 .zqcfg = 0x70073200ul,
114 .sdrfc = 0x00000C34ul,
119 /* Reset DDR3 PHY after PLL enabled */
122 if (board_is_k2g_gp()) {
123 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
124 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
125 } else if (board_is_k2g_ice()) {
126 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
127 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
133 inline int ddr3_get_size(void)