git.sur5r.net Git - u-boot/blob - board/toradex/colibri_imx7/colibri_imx7.c

   1 /*
   2  * Copyright (C) 2016 Toradex AG
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/crm_regs.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/mx7-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/gpio.h>
  13 #include <asm/imx-common/boot_mode.h>
  14 #include <asm/imx-common/iomux-v3.h>
  15 #include <asm/io.h>
  16 #include <common.h>
  17 #include <dm.h>
  18 #include <dm/platform_data/serial_mxc.h>
  19 #include <fsl_esdhc.h>
  20 #include <linux/sizes.h>
  21 #include <mmc.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <power/pmic.h>
  25 #include <power/rn5t567_pmic.h>
  26 #include <usb.h>
  27 #include <usb/ehci-ci.h>
  28 #include "../common/tdx-common.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  33         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  34
  35 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  36         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  39 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  40
  41 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  42
  43 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  44         PAD_CTL_DSE_3P3V_49OHM)
  45
  46 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  47
  48 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  49
  50 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  51
  52 int dram_init(void)
  53 {
  54         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  55
  56         return 0;
  57 }
  58
  59 static iomux_v3_cfg_t const uart1_pads[] = {
  60         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  61         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  63         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  64 };
  65
  66 static iomux_v3_cfg_t const usdhc1_pads[] = {
  67         MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73
  74         MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  75 };
  76
  77 #ifdef CONFIG_USB_EHCI_MX7
  78 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  79         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  80 };
  81 #endif
  82
  83 #ifdef CONFIG_NAND_MXS
  84 static iomux_v3_cfg_t const gpmi_pads[] = {
  85         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  90         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  91         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  92         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  93         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  94         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  95         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  96         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  97         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  98         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  99         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
 100 };
 101
 102 static void setup_gpmi_nand(void)
 103 {
 104         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 105
 106         /* NAND_USDHC_BUS_CLK is set in rom */
 107         set_clk_nand();
 108 }
 109 #endif
 110
 111 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 112         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX7D_PAD_SD3_STROBE__SD3_STROBE  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123
 124         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125 };
 126
 127 #ifdef CONFIG_VIDEO_MXS
 128 static iomux_v3_cfg_t const lcd_pads[] = {
 129         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 130         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 131         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 132         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 133         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 134         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 135         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 136         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 137         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 138         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 139         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 140         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 141         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 142         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 143         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 144         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 145         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 146         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 147         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 148         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 149         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 150         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 151 };
 152
 153 static iomux_v3_cfg_t const backlight_pads[] = {
 154         /* Backlight On */
 155         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         /* Backlight PWM<A> (multiplexed pin) */
 157         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 159 };
 160
 161 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 162 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 163
 164 static int setup_lcd(void)
 165 {
 166         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 167
 168         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 169
 170         /* Set BL_ON */
 171         gpio_request(GPIO_BL_ON, "BL_ON");
 172         gpio_direction_output(GPIO_BL_ON, 1);
 173
 174         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 175         gpio_request(GPIO_PWM_A, "PWM<A>");
 176         gpio_direction_output(GPIO_PWM_A, 0);
 177
 178         return 0;
 179 }
 180 #endif
 181
 182 #ifdef CONFIG_FEC_MXC
 183 static iomux_v3_cfg_t const fec1_pads[] = {
 184 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 185         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
 186 #else
 187         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188 #endif
 189         MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 190         MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 191         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 192         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 193         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 194         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL   | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 195         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 196         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 197         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 198 };
 199
 200 static void setup_iomux_fec(void)
 201 {
 202         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 203 }
 204 #endif
 205
 206 static void setup_iomux_uart(void)
 207 {
 208         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 209 }
 210
 211 #ifdef CONFIG_FSL_ESDHC
 212
 213 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 0)
 214
 215 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 216         {USDHC1_BASE_ADDR, 0, 4},
 217 };
 218
 219 int board_mmc_getcd(struct mmc *mmc)
 220 {
 221         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 222         int ret = 0;
 223
 224         switch (cfg->esdhc_base) {
 225         case USDHC1_BASE_ADDR:
 226                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 227                 break;
 228         }
 229
 230         return ret;
 231 }
 232
 233 int board_mmc_init(bd_t *bis)
 234 {
 235         int i, ret;
 236         /* USDHC1 is mmc0 */
 237         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 238                 switch (i) {
 239                 case 0:
 240                         imx_iomux_v3_setup_multiple_pads(
 241                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 242                         gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 243                         gpio_direction_input(USDHC1_CD_GPIO);
 244                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 245                         break;
 246                 default:
 247                         printf("Warning: you configured more USDHC controllers"
 248                                 "(%d) than supported by the board\n", i + 1);
 249                         return -EINVAL;
 250                 }
 251
 252                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 253                 if (ret)
 254                         return ret;
 255         }
 256
 257         return 0;
 258 }
 259 #endif
 260
 261 #ifdef CONFIG_FEC_MXC
 262 int board_eth_init(bd_t *bis)
 263 {
 264         int ret;
 265
 266         setup_iomux_fec();
 267
 268         ret = fecmxc_initialize_multi(bis, 0,
 269                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 270         if (ret)
 271                 printf("FEC1 MXC: %s:failed\n", __func__);
 272
 273         return ret;
 274 }
 275
 276 static int setup_fec(void)
 277 {
 278         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 279                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 280
 281 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 282         /*
 283          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 284          * and output it on the pin
 285          */
 286         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 287                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 288                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 289 #else
 290         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 291         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 292                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 293                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 294 #endif
 295
 296         return set_clk_enet(ENET_50MHz);
 297 }
 298
 299 int board_phy_config(struct phy_device *phydev)
 300 {
 301         if (phydev->drv->config)
 302                 phydev->drv->config(phydev);
 303         return 0;
 304 }
 305 #endif
 306
 307 int board_early_init_f(void)
 308 {
 309         setup_iomux_uart();
 310
 311         return 0;
 312 }
 313
 314 int board_init(void)
 315 {
 316         /* address of boot parameters */
 317         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 318
 319 #ifdef CONFIG_FEC_MXC
 320         setup_fec();
 321 #endif
 322
 323 #ifdef CONFIG_NAND_MXS
 324         setup_gpmi_nand();
 325 #endif
 326
 327 #ifdef CONFIG_VIDEO_MXS
 328         setup_lcd();
 329 #endif
 330
 331 #ifdef CONFIG_USB_EHCI_MX7
 332         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 333         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 334 #endif
 335
 336         return 0;
 337 }
 338
 339 #ifdef CONFIG_CMD_BMODE
 340 static const struct boot_mode board_boot_modes[] = {
 341         /* 4 bit bus width */
 342         {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
 343         {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
 344         {NULL, 0},
 345 };
 346 #endif
 347
 348 int board_late_init(void)
 349 {
 350 #ifdef CONFIG_CMD_BMODE
 351         add_board_boot_modes(board_boot_modes);
 352 #endif
 353
 354         return 0;
 355 }
 356
 357 #ifdef CONFIG_DM_PMIC
 358 int power_init_board(void)
 359 {
 360         struct udevice *dev;
 361         int reg, ver;
 362         int ret;
 363
 364
 365         ret = pmic_get("rn5t567", &dev);
 366         if (ret)
 367                 return ret;
 368         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 369         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 370
 371         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 372
 373         /* set judge and press timer of N_OE to minimal values */
 374         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 375
 376         return 0;
 377 }
 378
 379 void reset_cpu(ulong addr)
 380 {
 381         struct udevice *dev;
 382
 383         pmic_get("rn5t567", &dev);
 384
 385         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 386         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 387         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 388
 389         /*
 390          * Re-power factor detection on PMIC side is not instant. 1ms
 391          * proved to be enough time until reset takes effect.
 392          */
 393         mdelay(1);
 394 }
 395 #endif
 396
 397 int checkboard(void)
 398 {
 399         printf("Model: Toradex Colibri iMX7%c\n",
 400                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 401
 402         return 0;
 403 }
 404
 405 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 406 int ft_board_setup(void *blob, bd_t *bd)
 407 {
 408         return ft_common_board_setup(blob, bd);
 409 }
 410 #endif
 411
 412 #ifdef CONFIG_USB_EHCI_MX7
 413 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 414         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 415 };
 416
 417 int board_ehci_hcd_init(int port)
 418 {
 419         switch (port) {
 420         case 0:
 421                 break;
 422         case 1:
 423                 if (is_cpu_type(MXC_CPU_MX7S))
 424                         return -ENODEV;
 425
 426                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 427                                                  ARRAY_SIZE(usb_otg2_pads));
 428                 break;
 429         default:
 430                 return -EINVAL;
 431         }
 432         return 0;
 433 }
 434
 435 int board_usb_phy_mode(int port)
 436 {
 437         switch (port) {
 438         case 0:
 439                 if (gpio_get_value(USB_CDET_GPIO))
 440                         return USB_INIT_DEVICE;
 441                 else
 442                         return USB_INIT_HOST;
 443         case 1:
 444         default:
 445                 return USB_INIT_HOST;
 446         }
 447 }
 448 #endif