2 * Copyright 2015 Toradex, Inc.
5 * Copyright 2013 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-vf610.h>
14 #include <asm/arch/ddrmc-vf610.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
18 #include <fsl_esdhc.h>
25 #include "../common/tdx-common.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
32 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
33 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
35 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
36 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
38 #define USB_PEN_GPIO 83
39 #define USB_CDET_GPIO 102
41 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
43 { DDRMC_CR97_WRLVL_EN, 97 },
44 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
45 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
46 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
47 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
48 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
49 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
51 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
52 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
53 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
54 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
55 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
56 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
57 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
58 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
59 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
60 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
61 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
62 { DDRMC_CR126_PHY_RDLAT(8), 126 },
63 { DDRMC_CR132_WRLAT_ADJ(5) |
64 DDRMC_CR132_RDLAT_ADJ(6), 132 },
65 { DDRMC_CR137_PHYCTL_DL(2), 137 },
66 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
67 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
68 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
69 DDRMC_CR139_PHY_WRLV_DLL(3) |
70 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
71 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
72 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
73 DDRMC_CR143_RDLV_MXDL(128), 143 },
74 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
75 DDRMC_CR144_PHY_RDLV_DLL(3) |
76 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
77 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
78 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
79 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
80 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
81 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
82 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
84 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
85 DDRMC_CR154_PAD_ZQ_MODE(1) |
86 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
87 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
88 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
89 { DDRMC_CR158_TWR(6), 158 },
90 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
91 DDRMC_CR161_TODTH_WR(2), 161 },
96 static const iomux_v3_cfg_t usb_pads[] = {
97 VF610_PAD_PTD4__GPIO_83,
98 VF610_PAD_PTC29__GPIO_102,
103 static const struct ddr3_jedec_timings timings = {
106 .cke_inactive = 200000,
112 .tbst_int_interval = 0,
154 ddrmc_setup_iomux(NULL, 0);
156 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
157 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
162 static void setup_iomux_uart(void)
164 static const iomux_v3_cfg_t uart_pads[] = {
165 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
166 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
167 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
168 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
171 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
174 static void setup_iomux_enet(void)
176 static const iomux_v3_cfg_t enet0_pads[] = {
177 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
178 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
179 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
180 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
181 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
182 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
183 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
184 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
185 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
186 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
189 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
192 static void setup_iomux_i2c(void)
194 static const iomux_v3_cfg_t i2c0_pads[] = {
195 VF610_PAD_PTB14__I2C0_SCL,
196 VF610_PAD_PTB15__I2C0_SDA,
199 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
202 #ifdef CONFIG_NAND_VF610_NFC
203 static void setup_iomux_nfc(void)
205 static const iomux_v3_cfg_t nfc_pads[] = {
206 VF610_PAD_PTD23__NF_IO7,
207 VF610_PAD_PTD22__NF_IO6,
208 VF610_PAD_PTD21__NF_IO5,
209 VF610_PAD_PTD20__NF_IO4,
210 VF610_PAD_PTD19__NF_IO3,
211 VF610_PAD_PTD18__NF_IO2,
212 VF610_PAD_PTD17__NF_IO1,
213 VF610_PAD_PTD16__NF_IO0,
214 VF610_PAD_PTB24__NF_WE_B,
215 VF610_PAD_PTB25__NF_CE0_B,
216 VF610_PAD_PTB27__NF_RE_B,
217 VF610_PAD_PTC26__NF_RB_B,
218 VF610_PAD_PTC27__NF_ALE,
219 VF610_PAD_PTC28__NF_CLE
222 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
226 #ifdef CONFIG_FSL_DSPI
227 static void setup_iomux_dspi(void)
229 static const iomux_v3_cfg_t dspi1_pads[] = {
230 VF610_PAD_PTD5__DSPI1_CS0,
231 VF610_PAD_PTD6__DSPI1_SIN,
232 VF610_PAD_PTD7__DSPI1_SOUT,
233 VF610_PAD_PTD8__DSPI1_SCK,
236 imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
240 #ifdef CONFIG_VYBRID_GPIO
241 static void setup_iomux_gpio(void)
243 static const iomux_v3_cfg_t gpio_pads[] = {
244 VF610_PAD_PTA17__GPIO_7,
245 VF610_PAD_PTA20__GPIO_10,
246 VF610_PAD_PTA21__GPIO_11,
247 VF610_PAD_PTA30__GPIO_20,
248 VF610_PAD_PTA31__GPIO_21,
249 VF610_PAD_PTB0__GPIO_22,
250 VF610_PAD_PTB1__GPIO_23,
251 VF610_PAD_PTB6__GPIO_28,
252 VF610_PAD_PTB7__GPIO_29,
253 VF610_PAD_PTB8__GPIO_30,
254 VF610_PAD_PTB9__GPIO_31,
255 VF610_PAD_PTB12__GPIO_34,
256 VF610_PAD_PTB13__GPIO_35,
257 VF610_PAD_PTB16__GPIO_38,
258 VF610_PAD_PTB17__GPIO_39,
259 VF610_PAD_PTB18__GPIO_40,
260 VF610_PAD_PTB21__GPIO_43,
261 VF610_PAD_PTB22__GPIO_44,
262 VF610_PAD_PTC0__GPIO_45,
263 VF610_PAD_PTC1__GPIO_46,
264 VF610_PAD_PTC2__GPIO_47,
265 VF610_PAD_PTC3__GPIO_48,
266 VF610_PAD_PTC4__GPIO_49,
267 VF610_PAD_PTC5__GPIO_50,
268 VF610_PAD_PTC6__GPIO_51,
269 VF610_PAD_PTC7__GPIO_52,
270 VF610_PAD_PTC8__GPIO_53,
271 VF610_PAD_PTD31__GPIO_63,
272 VF610_PAD_PTD30__GPIO_64,
273 VF610_PAD_PTD29__GPIO_65,
274 VF610_PAD_PTD28__GPIO_66,
275 VF610_PAD_PTD27__GPIO_67,
276 VF610_PAD_PTD26__GPIO_68,
277 VF610_PAD_PTD25__GPIO_69,
278 VF610_PAD_PTD24__GPIO_70,
279 VF610_PAD_PTD9__GPIO_88,
280 VF610_PAD_PTD10__GPIO_89,
281 VF610_PAD_PTD11__GPIO_90,
282 VF610_PAD_PTD12__GPIO_91,
283 VF610_PAD_PTD13__GPIO_92,
284 VF610_PAD_PTB23__GPIO_93,
285 VF610_PAD_PTB26__GPIO_96,
286 VF610_PAD_PTB28__GPIO_98,
287 VF610_PAD_PTC30__GPIO_103,
288 VF610_PAD_PTA7__GPIO_134,
291 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
295 #ifdef CONFIG_FSL_ESDHC
296 struct fsl_esdhc_cfg esdhc_cfg[1] = {
300 int board_mmc_getcd(struct mmc *mmc)
302 /* eSDHC1 is always present */
306 int board_mmc_init(bd_t *bis)
308 static const iomux_v3_cfg_t esdhc1_pads[] = {
309 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
310 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
311 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
312 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
313 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
314 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
317 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
319 imx_iomux_v3_setup_multiple_pads(
320 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
322 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
326 static inline int is_colibri_vf61(void)
328 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
331 * Detect board type by Level 2 Cache: VF50 don't have any
334 return !!mscm->cpxcfg1;
337 static void clock_init(void)
339 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
340 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
341 u32 pfd_clk_sel, ddr_clk_sel;
343 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
344 CCM_CCGR0_UART0_CTRL_MASK);
345 #ifdef CONFIG_FSL_DSPI
346 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
348 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
349 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
350 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
351 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
352 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
353 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
354 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
355 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
356 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
357 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
358 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
359 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
360 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
361 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
362 CCM_CCGR7_SDHC1_CTRL_MASK);
363 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
364 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
365 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
366 CCM_CCGR10_NFC_CTRL_MASK);
369 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
372 #ifdef CONFIG_USB_EHCI
373 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
376 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
377 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
378 ANADIG_PLL5_CTRL_DIV_SELECT);
380 if (is_colibri_vf61()) {
381 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
382 ANADIG_PLL2_CTRL_POWERDOWN,
383 ANADIG_PLL2_CTRL_ENABLE |
384 ANADIG_PLL2_CTRL_DIV_SELECT);
387 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
388 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
390 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
391 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
393 /* See "Typical PLL Configuration" */
394 if (is_colibri_vf61()) {
395 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
396 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
398 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
399 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
402 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
403 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
404 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
405 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
406 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
407 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
408 CCM_CCSR_SYS_CLK_SEL(4));
410 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
411 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
412 CCM_CACRR_ARM_CLK_DIV(0));
413 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
414 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
415 CCM_CSCMR1_NFC_CLK_SEL(0));
416 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
417 CCM_CSCDR1_RMII_CLK_EN);
418 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
419 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
421 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
422 CCM_CSCDR3_NFC_PRE_DIV(5));
423 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
424 CCM_CSCMR2_RMII_CLK_SEL(2));
427 static void mscm_init(void)
429 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
432 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
433 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
436 int board_phy_config(struct phy_device *phydev)
438 if (phydev->drv->config)
439 phydev->drv->config(phydev);
444 int board_early_init_f(void)
452 #ifdef CONFIG_NAND_VF610_NFC
456 #ifdef CONFIG_VYBRID_GPIO
460 #ifdef CONFIG_FSL_DSPI
467 #ifdef CONFIG_BOARD_LATE_INIT
468 int board_late_init(void)
470 struct src *src = (struct src *)SRC_BASE_ADDR;
472 /* Default memory arguments */
473 if (!getenv("memargs")) {
474 switch (gd->ram_size) {
477 setenv("memargs", "mem=128M");
481 setenv("memargs", "mem=256M");
484 printf("Failed detecting RAM size.\n");
488 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
489 == SRC_SBMR2_BMOD_SERIAL) {
490 printf("Serial Downloader recovery mode, disable autoboot\n");
491 setenv("bootdelay", "-1");
496 #endif /* CONFIG_BOARD_LATE_INIT */
500 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
502 /* address of boot parameters */
503 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
506 * Enable external 32K Oscillator
508 * The internal clock experiences significant drift
509 * so we must use the external oscillator in order
510 * to maintain correct time in the hwclock
513 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
515 #ifdef CONFIG_USB_EHCI_VF
516 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
524 if (is_colibri_vf61())
525 puts("Board: Colibri VF61\n");
527 puts("Board: Colibri VF50\n");
532 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
533 int ft_board_setup(void *blob, bd_t *bd)
535 return ft_common_board_setup(blob, bd);
539 #ifdef CONFIG_USB_EHCI_VF
540 int board_ehci_hcd_init(int port)
542 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
546 /* USBC does not have PEN, also configured as USB client only */
549 gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
550 gpio_direction_output(USB_PEN_GPIO, 0);
556 int board_usb_phy_mode(int port)
561 * Port 0 is used only in client mode on Colibri Vybrid modules
562 * Check for state of USB client gpio pin and accordingly return
563 * USB_INIT_DEVICE or USB_INIT_HOST.
565 if (gpio_get_value(USB_CDET_GPIO))
566 return USB_INIT_DEVICE;
568 return USB_INIT_HOST;
570 /* Port 1 is used only in host mode on Colibri Vybrid modules */
571 return USB_INIT_HOST;
574 * There are only two USB controllers on Vybrid. Ideally we will
575 * not reach here. However return USB_INIT_HOST if we do.
577 return USB_INIT_HOST;