3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_85xx.h>
27 #include <asm/processor.h>
34 unsigned long refresh;
35 #endif /* CONFIG_TQM8548 */
38 typedef struct sdram_conf_s sdram_conf_t;
41 sdram_conf_t ddr_cs_conf[] = {
42 {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
43 {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
44 {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
46 #else /* !CONFIG_TQM8548 */
47 sdram_conf_t ddr_cs_conf[] = {
48 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
49 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
50 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
51 {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
53 #endif /* CONFIG_TQM8548 */
55 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
57 int cas_latency (void);
60 * Autodetect onboard DDR SDRAM on 85xx platforms
62 * NOTE: Some of the hardcoded values are hardware dependant,
63 * so this should be extended for other future boards
66 long int sdram_setup (int casl)
69 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
71 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
72 #else /* !CONFIG_TQM8548 */
73 unsigned long cfg_ddr_timing1;
74 unsigned long cfg_ddr_mode;
75 #endif /* CONFIG_TQM8548 */
78 * Disable memory controller.
84 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
85 ddr->cs0_config = ddr_cs_conf[0].reg;
86 ddr->timing_cfg_3 = 0x00010000;
88 /* TIMING CFG 1, 533MHz
98 ddr->timing_cfg_1 = 0x4C47A432;
100 /* TIMING CFG 2, 533MHz
104 * RD_TO_PRE: 2 Clocks
105 * WR_DATA_DELAY: 1/2 Clock
107 * FOUR_ACT: 13 Clocks
109 ddr->timing_cfg_2 = 0x3318484D;
111 /* DDR SDRAM Mode, 533MHz
112 * MRS: Extended Mode Register
113 * OUT: Outputs enabled
118 * Posted CAS: 3 Clocks
119 * ODS: reduced strength
126 * CAS latency: 4 Clocks
130 ddr->sdram_mode = 0x439E0642;
132 /* DDR SDRAM Interval, 533MHz
133 * REFINT: 1040 Clocks
136 ddr->sdram_interval = (1040 << 16) | 0x100;
139 * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
140 * DDR IO receiver must be set to an acceptable bias point by modifying
143 if (SVR_REV (get_svr ()) < 0x20) {
144 gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
148 * FRC_SR: normal mode
149 * SR_IE: no self-refresh interrupt
150 * DLL_RST_DIS: don't care, leave at reset value
151 * DQS_CFG: differential DQS signals
152 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
153 * LVWx_CFG: don't care, leave at reset value
154 * NUM_PR: 1 refresh will be issued at a time
155 * DM_CFG: don't care, leave at reset value
156 * D_INIT: no data initialization
158 ddr->sdram_cfg_2 = 0x04401000;
161 * MRS: Extended Mode Register 2
163 ddr->sdram_mode_2 = 0x8000C000;
165 /* DDR SDRAM CLK CNTL
166 * CLK_ADJUST: 1/2 Clock 0x02000000
167 * CLK_ADJUST: 5/8 Clock 0x02800000
169 ddr->sdram_clk_cntl = 0x02800000;
171 /* wait for clock stabilization */
172 asm ("sync;isync;msync");
175 /* DDR SDRAM CLK CNTL
177 * SREN: don't care, leave at reset value
178 * ECC_EN: no error report
179 * RD_EN: no register DIMMs
181 * DYN_PWR: no power management
182 * 32_BE: don't care, leave at reset value
184 * NCAP: don't care, leave at reset value
186 * BA_INTLV_CTL: no interleaving
187 * x32_EN: x16 organization
188 * PCHB8: MA[10] for auto-precharge
189 * HSE: half strength for single and 2-layer stacks
190 * (full strength for 3- and 4-layer stacks no yet considered)
192 * BI: automatic initialization
194 ddr->sdram_cfg = 0x83000008;
195 asm ("sync; isync; msync");
198 #else /* !CONFIG_TQM8548 */
201 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
202 cfg_ddr_mode = 0x40020002 | (2 << 4);
206 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
207 cfg_ddr_mode = 0x40020002 | (6 << 4);
212 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
213 cfg_ddr_mode = 0x40020002 | (3 << 4);
217 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
218 ddr->cs0_config = ddr_cs_conf[0].reg;
219 ddr->timing_cfg_1 = cfg_ddr_timing1;
220 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
221 ddr->sdram_mode = cfg_ddr_mode;
222 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
223 ddr->err_disable = 0x0000000D;
225 asm ("sync; isync; msync");
228 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
229 asm ("sync; isync; msync");
231 #endif /* CONFIG_TQM8548 */
233 for (i = 0; i < N_DDR_CS_CONF; i++) {
234 ddr->cs0_config = ddr_cs_conf[i].reg;
236 if (get_ram_size (0, ddr_cs_conf[i].size) ==
237 ddr_cs_conf[i].size) {
239 * size detected -> set Chip Select Bounds Register
241 ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
247 #ifdef CONFIG_TQM8548
248 if (i < N_DDR_CS_CONF) {
249 /* Adjust refresh rate for DDR2 */
251 ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
253 ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
254 (ddr_cs_conf[i].refresh & 0x0000F000);
256 return ddr_cs_conf[i].size;
258 #endif /* CONFIG_TQM8548 */
260 /* return size if detected, else return 0 */
261 return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
264 void board_add_ram_info (int use_default)
269 casl = CONFIG_DDR_DEFAULT_CL;
271 casl = cas_latency ();
289 long int initdram (int board_type)
294 #if defined(CONFIG_DDR_DLL)
296 * This DLL-Override only used on TQM8540 and TQM8560
299 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
305 * Work around to stabilize DDR DLL
307 gur->ddrdllcr = 0x81000000;
308 asm ("sync; isync; msync");
310 while (gur->ddrdllcr != 0x81000100) {
311 gur->devdisr = gur->devdisr | 0x00010000;
312 asm ("sync; isync; msync");
313 for (i = 0; i < x; i++)
315 gur->devdisr = gur->devdisr & 0xfff7ffff;
316 asm ("sync; isync; msync");
322 casl = cas_latency ();
323 dram_size = sdram_setup (casl);
324 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
326 * Try again with default CAS latency
328 puts ("Problem with CAS lantency");
329 board_add_ram_info (1);
330 puts (", using default CL!\n");
331 casl = CONFIG_DDR_DEFAULT_CL;
332 dram_size = sdram_setup (casl);
339 #if defined(CFG_DRAM_TEST)
342 uint *pstart = (uint *) CFG_MEMTEST_START;
343 uint *pend = (uint *) CFG_MEMTEST_END;
346 printf ("SDRAM test phase 1:\n");
347 for (p = pstart; p < pend; p++)
350 for (p = pstart; p < pend; p++) {
351 if (*p != 0xaaaaaaaa) {
352 printf ("SDRAM test fails at: %08x\n", (uint) p);
357 printf ("SDRAM test phase 2:\n");
358 for (p = pstart; p < pend; p++)
361 for (p = pstart; p < pend; p++) {
362 if (*p != 0x55555555) {
363 printf ("SDRAM test fails at: %08x\n", (uint) p);
368 printf ("SDRAM test passed.\n");